Worked on the OpenXiangShan/GEM5 repository to enhance the RISC-V ISA decoder, focusing on improving checkpoint and restore fidelity as well as expanding floating-point support. Leveraged C++ and deep knowledge of computer architecture to implement CSR state enablement for accurate state capture and restoration during simulation. Developed decoding for the new pack instruction and extended Zfa support by adding fround, froundnx, and fli instructions across single, double, and half-precision, with correct status and VM handling. These enhancements reduced simulation drift during state migration and enabled more reliable floating-point workloads in GEM5’s RISC-V simulation environment.