Worked on the pulp-platform/spatz repository to enhance the reliability of the register file by implementing resettable registers and refactoring the existing design. The approach involved removing a problematic latch resetting signal, which previously posed risks of data corruption during reset events. By focusing on reset behavior, the work reduced potential edge cases related to system restarts and improved overall data integrity. Leveraging SystemVerilog and applying principles of digital logic and hardware design, the developer delivered a targeted feature that addressed a specific reliability concern. The contribution reflects a focused engineering effort to improve hardware robustness within a short project period.