During March 2026, Dishaen contributed to the pulp-platform/spatz repository by refactoring the register file to implement resettable registers, addressing reliability and data integrity concerns during system resets. Using SystemVerilog and applying digital logic design principles, Dishaen removed a problematic latch resetting signal that previously risked data corruption, thereby reducing potential edge cases related to restart scenarios. The work focused on hardware design improvements, ensuring that the register file maintained consistent behavior across resets. While the contribution was limited to a single feature over one month, it demonstrated a targeted approach to enhancing reset functionality and robustness within the hardware module.