During June 2025, Pei-Ting Kuo refactored the sm_bus logic in the stage_top.v module for the vic9112/final_project_2025 repository, focusing on improving data handling and transmission reliability. Leveraging expertise in Digital Logic Design and Hardware Design with Verilog, Pei-Ting introduced a state machine to the sm_buffer for accurate tracking of data occupancy and implemented a counter to enable sequential, orderly data output. This engineering work enhanced the module’s ability to process and transmit data streams efficiently, improving throughput and reducing the risk of data loss. The contribution demonstrated thoughtful architectural changes within a focused project scope.