Worked on enhancing data handling within the vic9112/final_project_2025 repository by refactoring the sm_bus logic in the stage_top.v module. Applied expertise in Digital Logic Design and Verilog to introduce a state machine for the sm_buffer, enabling accurate tracking of data occupancy and improving the reliability of data validity signaling. Added a counter mechanism to support sequential and orderly data output, which increased the throughput and robustness of the data stream. The technical approach focused on hardware design principles to reduce the risk of data loss and ensure more efficient data processing, resulting in a more reliable data transmission pipeline.