Worked on the redis/redis repository to optimize performance in a core hashing path, focusing on architecture-specific improvements for RISC-V platforms. Developed and implemented an enhancement to SipHash by enabling unaligned memory access using the RISC-V Zicclsm extension, targeting increased throughput for RISC-V workloads. The work involved low-level C programming and embedded systems expertise, applying performance optimization techniques tailored to the RISC-V architecture. This contribution not only improved hashing efficiency but also established a foundation for future platform-optimized operations within Redis. The approach demonstrated a methodical application of architecture-aware optimization, addressing both immediate performance needs and long-term extensibility.