During their time at Antmicro, Mszelwiga focused on improving the reliability of parameter handling in the YosysHQ/yosys repository. They addressed a bug in the setundef pass, where parameter bits were not set correctly, by refining the underlying logic using Verilog and C++. To ensure the fix remained robust, Mszelwiga implemented a dedicated regression test with Yosys scripting, enhancing test coverage and safeguarding against future regressions. Their work required a solid understanding of hardware description languages and pass development, and contributed to more stable synthesis flows for parameterized designs. The solution was validated across the repository for consistent parameter manipulation.