Worked on the YosysHQ/yosys repository to address a reliability issue in parameter handling within the setundef pass. Focused on correcting the incorrect setting of parameter bits, the solution involved modifying the pass logic using C++ and Verilog, ensuring accurate manipulation of parameterized designs. To safeguard against future regressions, a dedicated regression test was implemented with Yosys scripting and SystemVerilog, expanding test coverage for bit-level parameter behavior. The changes were validated across the synthesis flow to confirm stable operation, reducing the risk of mis-synthesis in parameterized modules and improving the robustness of hardware description language workflows in Yosys.