During March 2025, contributed to the intel/lkvs repository by enhancing architecture-specific test coverage for performance monitoring units. Developed and integrated seven new automated test cases targeting ARCH PEBS PMU, focusing on validating CPUID logic, general-purpose and XMM register groups, and various counter configurations. Leveraged shell scripting and system programming skills to design tests that improve validation reliability and qualification readiness for the target architecture. Emphasized architecture-aware test design and register-level validation, ensuring comprehensive coverage of performance monitoring features. The work strengthened the testing framework and supported robust performance monitoring validation, utilizing shell and testing frameworks to achieve these goals.