Developed a generalizable Partition Analysis Pass for Enhanced Scheduling in the intel/intel-xpu-backend-for-triton repository, focusing on improving partition scheduling for complex GPU workloads. The approach leveraged compiler design principles and MLIR, utilizing a data flow graph and heuristic-driven partition merging to enable incremental scheduling improvements while preserving existing behavior. C++ was used to implement the new pass, which serves as a drop-in replacement and maintains stability across critical workloads. Expanded and updated test coverage ensured no performance regressions, supporting maintainability and future enhancements. The work emphasized performance optimization and resource utilization without introducing regressions or disrupting established functionality.