Worked on the intel/rohd-bridge repository to enhance SystemVerilog net generation by introducing explicit intermediate net naming for connectPorts. Developed an optional intermediateSignalName parameter, enabling precise naming of intermediate nets and automatic uniquification to prevent naming collisions in complex hardware topologies. Leveraged Dart and SystemVerilog, and applied backend development skills to ensure that existing nets are reused for fan-out scenarios, improving efficiency in generated designs. Comprehensive unit tests were implemented to validate signal propagation and naming across various connection types, resulting in clearer, collision-free net structures and improved maintainability, with a strong emphasis on test-driven development practices.