Worked on enhancing SystemVerilog feature expressiveness in the llvm/circt repository by introducing support for arbitrary expression case patterns within case statements. Developed the CaseExprPattern construct and integrated it into the CaseOp parsing, printing, and emission flows, enabling more flexible and future-proof pattern matching throughout the SystemVerilog lowering pipeline. Leveraged C++ and MLIR to implement these changes, focusing on compiler development and dialect design. Comprehensive tests were added to demonstrate the new functionality and ensure regression coverage. This work strengthened the repository’s readiness for broader SystemVerilog feature support and improved maintainability within the LLVM-based circt infrastructure.