Worked on the chipsalliance/Cores-VeeR-EL2 repository to enhance hardware verification and reliability over a two-month period. Introduced assertion-based checks in the DCLS path using SystemVerilog, enabling early detection of delay issues and reducing debugging time. Modified Makefile infrastructure to ensure Verilator simulations consistently run with assertions enabled, improving test coverage in CI environments. Addressed a critical bug in the lockstep module by correcting assertion handling syntax and preventing delay underflow when the delay count is zero. These efforts strengthened deterministic execution and timing stability, leveraging skills in SystemVerilog, Verilator, and hardware design to improve core robustness and maintainability.