During February 2025, Daicheng Rong enhanced RISC-V capability detection in the openssl/openssl repository by integrating dl_hwcap to improve ZVK* feature reporting. He implemented new C definitions and low-level logic to determine vector instruction availability at runtime, enabling more accurate hardware capability detection for RISC-V architectures. This work allows OpenSSL to select optimized code paths based on actual hardware features, improving reliability in cross-architecture builds. Daicheng applied embedded systems and system programming skills, focusing on precise feature detection rather than bug fixes. The depth of his contribution lies in the careful integration of hardware introspection within a complex codebase.