Month: 2025-12 | Repository: nrfconnect/sdk-zephyr Summary: Concluded the year with a critical stability improvement in the SAMD5X path by aligning the DAC clock source with the ADC clock, ensuring operation stays within the DAC's maximum speed. This fix reduces clock-domain risk and enhances reliability for DAC functionality within Zephyr on SAMD5X devices. Key achievements delivered: - Fixed SAMD5X DAC generic clock source by aligning with the ADC clock (0x2) to satisfy maximum speed constraints. - DTS update in Atmel SAM0 to reflect the corrected DAC clock source, preventing misconfiguration at runtime. - Verified clock alignment against Microchip auto-generated code to ensure register consistency and correctness. - Code change documented and committed (dts: atmel: sam0: fix dac generic clock source) with commit 80801d81bba00e0a06ea287d8b3e04b0993880b2. Impact and business value: - Improves DAC stability and predictability, reducing field failures related to clock misconfiguration. - Strengthens platform reliability for audio/DAC workflows and time-critical operations on SAMD5X in Zephyr. - Supports safer future optimizations of the clock tree by establishing a correct, vendor-aligned clock source reference. Technologies/skills demonstrated: - Embedded clock domain alignment and stabilization - Device Tree (DTS) changes and hardware clock configuration - Cross-reference validation against vendor auto-generated code - Change control and traceability through commit documentation and signing