During October 2024, Demin Han focused on improving the accuracy of RISC-V interrupt handling in the OpenXiangShan/riscv-isa-sim repository. He addressed a critical bug in the simulator’s interrupt enable logic by correcting a bit shift that determined the starting position for non-standard interrupts. This low-level change, implemented in C++ and validated through targeted tests and code review, enhanced the simulator’s reliability for interrupt-driven workloads by ensuring proper interrupt priority and more accurate simulation results. Drawing on his expertise in embedded systems and RISC-V architecture, Demin’s work reduced the risk of edge-case failures in complex processor simulation scenarios.