conneroisu/sfhw-proj2
Nov 2024 – Nov 2024
1 Month active
Languages Used
VHDL
Technical Skills
Digital Logic DesignHardware DesignProcessor ArchitectureTest Bench DevelopmentVHDL
dmvp01
PROFILE
Dmvp01
During November 2024, Connor Oisu developed the EX/MEM pipeline register for the CPU datapath in the conneroisu/sfhw-proj2 repository. He implemented this feature using VHDL, applying his skills in digital logic design and processor architecture to ensure accurate data transfer and control signal handling between the Execute and Memory stages. To verify the design, Connor created a dedicated test bench, which improved verification coverage and helped identify potential timing and control issues early in the development process. This work contributed to the overall integrity of the pipeline, reflecting a focused and methodical approach to hardware design and validation.
Overall Statistics
Feature vs Bugs
100%Features
Repository Contributions
1Total
Bugs
0
Commits
1
Features
1
Lines of code
234
Activity Months1
Your Network
6 people
Work History
November 2024
1 Commits • 1 Features
Nov 1, 2024November 2024 monthly summary for conneroisu/sfhw-proj2: Delivered the EX/MEM pipeline register in the CPU datapath with an accompanying test bench to verify data transfer and control signal handling between the Execute and Memory stages. This work enhances pipeline integrity, improves verification coverage, and reduces risk in the datapath by catching timing and control-signal issues early.
1 Commits • 1 Features
Nov 1, 2024November 2024 monthly summary for conneroisu/sfhw-proj2: Delivered the EX/MEM pipeline register in the CPU datapath with an accompanying test bench to verify data transfer and control signal handling between the Execute and Memory stages. This work enhances pipeline integrity, improves verification coverage, and reduces risk in the datapath by catching timing and control-signal issues early.
November 2024
Activity
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Quality Metrics
Correctness100.0%
Maintainability100.0%
Architecture100.0%
Performance100.0%
AI Usage20.0%
Skills & Technologies
Programming Languages
VHDL
Technical Skills
Digital Logic DesignHardware DesignProcessor ArchitectureTest Bench DevelopmentVHDL
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