Developed a configurable SystemC time resolution feature for the antmicro/verilator repository, enabling users to select simulation time steps such as 10 or 100 for improved accuracy and performance control in SystemC workloads. The implementation involved C++ development and SystemC integration, with a focus on commit-based traceability and detailed issue referencing to ensure maintainability. By allowing finer granularity in simulation timing, the work enhanced validation fidelity and provided more options for performance tuning, supporting earlier detection of timing issues. The approach demonstrated proficiency in C++ and Python scripting, as well as test-driven development practices within a collaborative open-source environment.