During July 2025, Emanuele Zelioli focused on improving hardware verification reliability for the pulp-platform/croc repository by addressing a critical testbench timing synchronization issue. He identified that stimuli application and sampling were previously tied to the system clock, which caused synchronization problems when the JTAG clock frequency differed. By redesigning the testbench to base timing on the JTAG clock period, Emanuele eliminated cross-frequency timing issues and improved test stability. This work demonstrated his proficiency in SystemVerilog, hardware design, and verification, resulting in more reproducible test results and smoother integration with diverse hardware clocks. The solution reflects a deep understanding of embedded timing.