Worked on the Xilinx/llvm-aie repository to modularize vector instruction patterns by target, focusing on the separation of VBOR and VBAND selection patterns into target-specific files. This approach improved the maintainability and modularity of vector instruction definitions, reducing cross-target dependencies and enabling more effective architecture-specific optimizations. Leveraged skills in compiler design, low-level programming, and vector processing, utilizing TableGen to refactor and organize instruction patterns for the AIE architecture. The work supported long-term project stability by aligning pattern definitions with target boundaries, facilitating easier integration of new vector types and contributing to the overall reliability of the codebase.