Fei Hours worked on the SpinalHDL/SpinalHDL repository, focusing on stabilizing the memory interface with AXI-Lite4 MemBus by addressing a critical bug in the RegIf write address handling. Using Scala and hardware description language skills, Fei refactored the write-address path to ensure correct address mapping during write operations, directly improving the reliability of bus protocol implementation. The work included expanding regression test coverage to catch edge cases and prevent future regressions, enhancing verification processes. Although the period involved only one bug fix and no new features, the depth of the solution contributed to more robust and production-ready hardware integration.