Worked on enhancing the SpinalHDL/SpinalHDL repository by stabilizing the memory interface through a targeted bug fix in the AXI-Lite4 MemBus integration. Addressed a critical issue in RegIf write address handling by refactoring the write-address path to ensure accurate address mapping during write operations. Leveraged skills in bus protocol implementation, hardware description language, and verification, using Scala to implement and validate the solution. Expanded regression test coverage to capture edge cases and prevent future regressions, thereby improving the robustness and reliability of the memory interface. The work reduced the risk of misaddressed writes and potential production defects.