YosysHQ/yosys
Apr 2026 – Apr 2026
1 Month active
Languages Used
Verilog
Technical Skills
FPGA developmentVeriloghardware design
George Haworth
PROFILE
George Haworth
Worked on the YosysHQ/yosys repository, focusing on FPGA development and hardware design using Verilog. Addressed a critical bug in the RAMB36E1/E2 single dual-port (SDP) parity port mapping, correcting a width condition from 71 to 72 to prevent silent data overwrites. This fix improved data integrity and reliability of parity paths across multiple FPGA families, including Artix-7, Kintex-7, Virtex-7, and UltraScale+ devices. The solution ensured consistent parity logic in both xc6v and xcu mappings, aligning with DIBDI/DINBDIN parity handling. Demonstrated attention to detail and deep understanding of hardware description and FPGA architecture.
Overall Statistics
Feature vs Bugs
0%Features
Repository Contributions
1Total
Bugs
1
Commits
1
Features
0
Lines of code
4
Activity Months1
Your Network
87 peopleWork History
April 2026
1 Commits
Apr 1, 2026April 2026 monthly summary for repository YosysHQ/yosys. Delivered a critical bug fix addressing the RAMB36E1/E2 SDP parity port mapping issue, improving data integrity and reliability of parity paths across FPGA families. The fix corrects a width condition typo (previously PORT_W_WIDTH == 71; now correctly 72), preventing silent data overwrites and ensuring proper data handling across RAMB36E1/E2 templates. The change applies to both xc6v (RAMB36E1) and xcu (RAMB36E2) mappings and aligns with DIBDI/DINBDIN parity logic on related lines, affecting Artix-7/Kintex-7/Virtex-7/UltraScale+ devices. Commit reference for traceability: aba5b279c6ea3c7ef0867f43d2f7d8dc23d9f440.
1 Commits
Apr 1, 2026April 2026 monthly summary for repository YosysHQ/yosys. Delivered a critical bug fix addressing the RAMB36E1/E2 SDP parity port mapping issue, improving data integrity and reliability of parity paths across FPGA families. The fix corrects a width condition typo (previously PORT_W_WIDTH == 71; now correctly 72), preventing silent data overwrites and ensuring proper data handling across RAMB36E1/E2 templates. The change applies to both xc6v (RAMB36E1) and xcu (RAMB36E2) mappings and aligns with DIBDI/DINBDIN parity logic on related lines, affecting Artix-7/Kintex-7/Virtex-7/UltraScale+ devices. Commit reference for traceability: aba5b279c6ea3c7ef0867f43d2f7d8dc23d9f440.
April 2026
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Quality Metrics
Correctness100.0%
Maintainability100.0%
Architecture100.0%
Performance100.0%
AI Usage20.0%
Skills & Technologies
Programming Languages
Verilog
Technical Skills
FPGA developmentVeriloghardware design
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