levizh/rt-thread
Feb 2026 – Feb 2026
1 Month active
Languages Used
CMarkdown
Technical Skills
C programmingRISC-V architectureRTOS developmentdocumentationembedded systemslow-level programming
shuta.lst
PROFILE
Shuta.lst
Shuta contributed to the levizh/rt-thread repository by implementing RISC-V Svpbmt extension support on the C908 architecture, enhancing memory management with updated MMU features and PTE macros. He introduced system initialization, interrupt handling, and memory management for the Xuantie C908x, focusing on low-level C programming and embedded systems. Shuta also corrected documentation for XuanTie processors, ensuring accuracy in CPU type references and QEMU execution commands. His work addressed platform-wide memory protection and improved initialization consistency, coordinating macro definitions across board support packages. The depth of his contributions reflects strong expertise in RTOS development, RISC-V architecture, and technical documentation.
Overall Statistics
Feature vs Bugs
67%Features
Repository Contributions
6Total
Bugs
1
Commits
6
Features
2
Lines of code
5,561
Activity Months1
Your Network
420 peopleSame Organization
@alibaba-inc.com291
Shared Repositories
129
Work History
February 2026
6 Commits • 2 Features
Feb 1, 2026February 2026 monthly summary for levizh/rt-thread: Implemented RISC-V Svpbmt Extension support on C908 with MMU enhancements and PTE macro updates; added Xuantie C908x architecture support (system init, interrupt handling, and memory management); corrected XuanTie processor documentation; ensured consistent Svpbmt-related macro definitions across BSPs. Focused on delivering features that unlock platform-wide memory protection capabilities, improve initialization and IRQ handling, and maintain accurate docs for users.
6 Commits • 2 Features
Feb 1, 2026February 2026 monthly summary for levizh/rt-thread: Implemented RISC-V Svpbmt Extension support on C908 with MMU enhancements and PTE macro updates; added Xuantie C908x architecture support (system init, interrupt handling, and memory management); corrected XuanTie processor documentation; ensured consistent Svpbmt-related macro definitions across BSPs. Focused on delivering features that unlock platform-wide memory protection capabilities, improve initialization and IRQ handling, and maintain accurate docs for users.
February 2026
Activity
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Quality Metrics
Correctness93.4%
Maintainability90.0%
Architecture93.4%
Performance90.0%
AI Usage23.4%
Skills & Technologies
Programming Languages
CMarkdown
Technical Skills
C programmingRISC-V architectureRTOS developmentdocumentationembedded systemslow-level programmingmemory management
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