During August 2022, Jonas Jensen extended the Xilinx DSP capabilities in the YosysHQ/yosys repository by implementing subtraction support in the preadder component of the Xilinx DSP library. Using C++ and leveraging expertise in DSP design and hardware description languages, Jonas enabled both addition and subtraction within DSP packing for Xilinx FPGA targets. This enhancement broadened the design space for DSP-heavy pipelines and reduced the need for workaround logic, improving compatibility with existing toolchains. The work was delivered as a single, well-scoped commit, ensuring traceability and maintainability for future development while addressing a specific gap in the DSP flow.