rapidstream-org/rapidstream-tapa
Nov 2024 – Aug 2025
10 Months active
Languages Used
BATSBashBazelC++DockerfilePythonShellStarlark
Technical Skills
BazelBuild System ConfigurationBuild SystemsC++C++ library developmentCI/CD
Blaok
PROFILE
Blaok
Over ten months, Blaok contributed to rapidstream-org/rapidstream-tapa by modernizing its hardware-software co-design stack, focusing on vendor-agnostic Verilog parsing, robust build automation, and scalable test infrastructure. Blaok refactored core modules to unify backend handling, introduced type-safe interfaces, and streamlined cosimulation and synthesis flows using Python and C++. By removing legacy dependencies and implementing static analysis with tools like Bazel and pyright, Blaok improved maintainability and early bug detection. Their work included packaging optimizations, enhanced CI/CD reliability, and modular code generation, resulting in a more reliable, testable, and developer-friendly platform for FPGA and hardware acceleration workflows.
Overall Statistics
Feature vs Bugs
73%Features
Repository Contributions
294Total
Bugs
33
Commits
294
Features
89
Lines of code
16,036
Activity Months10
Your Network
6 people
Work History
August 2025
17 Commits • 3 Features
Aug 1, 2025Concise monthly summary for August 2025 focusing on delivering solid foundational improvements in rapidstream-tapa. The month centered on architectural modernization for Verilog parsing, extensive type safety and static analysis enhancements, and streamlined program/argument handling to improve reliability and developer velocity. These efforts establish a vendor-agnostic, maintainable parsing backbone while enabling earlier issue detection and safer future refactors.
17 Commits • 3 Features
Aug 1, 2025Concise monthly summary for August 2025 focusing on delivering solid foundational improvements in rapidstream-tapa. The month centered on architectural modernization for Verilog parsing, extensive type safety and static analysis enhancements, and streamlined program/argument handling to improve reliability and developer velocity. These efforts establish a vendor-agnostic, maintainable parsing backbone while enabling earlier issue detection and safer future refactors.
August 2025
July 2025
16 Commits • 3 Features
Jul 1, 2025July 2025 monthly summary for rapidstream-org/rapidstream-tapa. Delivered cross-backend Verilog frontend improvements, improved synthesis reliability, and strengthened testing/CI, with a focus on business value, maintainability, and scalable architecture.
July 2025
16 Commits • 3 Features
Jul 1, 2025July 2025 monthly summary for rapidstream-org/rapidstream-tapa. Delivered cross-backend Verilog frontend improvements, improved synthesis reliability, and strengthened testing/CI, with a focus on business value, maintainability, and scalable architecture.
June 2025
45 Commits • 13 Features
Jun 1, 2025June 2025 monthly update for rapidstream-tapa focused on stabilizing and modernizing the libtapa stack, improving build hygiene, expanding test coverage, and standardizing scaffolding. The work delivers clearer ownership of the queue/FRT path, stronger packaging controls, and scalable tooling for future sprints. Overall, the month reduced risk, improved maintainability, and reinforced business value through robust test suites and consistent build artifacts.
45 Commits • 13 Features
Jun 1, 2025June 2025 monthly update for rapidstream-tapa focused on stabilizing and modernizing the libtapa stack, improving build hygiene, expanding test coverage, and standardizing scaffolding. The work delivers clearer ownership of the queue/FRT path, stronger packaging controls, and scalable tooling for future sprints. Overall, the month reduced risk, improved maintainability, and reinforced business value through robust test suites and consistent build artifacts.
June 2025
May 2025
18 Commits • 4 Features
May 1, 2025May 2025 performance summary for rapidstream-tapa: delivered cosimulation tooling, doctest infrastructure, path-based modernization, and FPGA runtime data handling improvements; packaging and build optimizations enabled easier distribution and faster iteration.
May 2025
18 Commits • 4 Features
May 1, 2025May 2025 performance summary for rapidstream-tapa: delivered cosimulation tooling, doctest infrastructure, path-based modernization, and FPGA runtime data handling improvements; packaging and build optimizations enabled easier distribution and faster iteration.
April 2025
51 Commits • 18 Features
Apr 1, 2025April 2025 monthly summary for rapidstream-tapa: Highlights across features, bugs fixed, and architecture/CI improvements delivering stronger determinism, packaging modularity, and reliable builds. This month focused on code cleanliness, performance, and packaging reliability to accelerate release cycles.
51 Commits • 18 Features
Apr 1, 2025April 2025 monthly summary for rapidstream-tapa: Highlights across features, bugs fixed, and architecture/CI improvements delivering stronger determinism, packaging modularity, and reliable builds. This month focused on code cleanliness, performance, and packaging reliability to accelerate release cycles.
April 2025
March 2025
50 Commits • 17 Features
Mar 1, 2025March 2025 (rapidstream-tapa): Key platform improvements and reliability enhancements across Tapac, libtapa, and the build/test pipeline. The month delivered substantive refactors, new tooling integrations, and CI/quality improvements that collectively boost maintainability, hardware-software co-design reliability, and time-to-value for customers relying on TAP-accelerated flows. Key features delivered: - Tapac: Core port handling refactor and FSM integration: added FSM ap_ctrl ports, consolidated add_ports usage in add_m_axi, and streamlined port removal to simplify codegen and port lifecycle management. (Commits include: cdc7ba33, 958fc60b, 1470f4a) - Tapac: PyslangRewriter and pyslang-powered Module API: introduced PyslangRewriter, and expanded Module API with add_instance/del_instances/add_rs_pragmas/add_logics, template generation, and pyslang-enabled defaults for streamlined codegen. (Commits include: b978eb90, d52f213d, d5a77a5f, 7ed03f1e, 06d7ef38, e93abfd2, a8a6c05b, 3c591a5c, 957b5020, 201f2be7) - IO/Module constructs with pyslang: added IOPort, Module.ports, Module.signals, Module.params support via pyslang, enabling richer hardware interface modeling. (Commits include: 69d8ac94, 0a9e6912, bcaacd79, 4d0b2554) - Build and tooling improvements: Bazel build enhancements to treat output_file as attr.output, explicitly set work_dir, and propagate vitis_mode to tapa_xo; CI/workflow cleanup to remove iverilog dependency and adjust wrangler R2 CLI. (Commits include: bb88133d, 98585617, d96c3f64, d0a348b30, 39d80499, fd0c9b11) - Code quality, tests, and refactors: labelling and pruning of unused code, test coverage expansions (e.g., labeling PE loops, pragma deletion; do-not-share-project-dir test fixes), and broader refactors to reuse codegen and improve module/item management. (Commits include: 8c14a974, 792fa26a, 4c695b5c, 8f12eb8c, 6328ba1a, 0a3155f8) Major bugs fixed: - Tapac argument and port handling fixes: skip nonexistent arguments, fix repeated port_names access, address missing ports with --no-vitis-mode, and ensure FSM pragma initialization occurs. (Commits include: 4c7e5bb5, 372738db, 1e2fa5ec, 67bc4d80) - Libtapa: Correct argument access order to preserve sequencing reliability. (Commit: c1e53771) - LLVM build hygiene: fix -Wno-unused-variable handling for cleaner warnings. (Commit: deecd151) - Test isolation and memory layout fixes: ensure test(stream-top) does not share project dir; fix host memory layout in cannon tests; RNG usage and test variants updated. (Commits: d9910a99, 5b674957, f691abdd) - Tapac teardown and parameter parsing cleanup: ensure del_port behavior does not delete header ports and remove problematic parameter statements via pyslang. (Commits: 02346273, 6d458216) - CI/docs cleanup: remove iverilog as dependency and align docs/CLI accordingly. (Commits: d0a348b3, 39d80499, fd0c9b11) Overall impact and accomplishments: - Significantly improved Tapac reliability and flexibility for hardware-software co-design, with safer port management, FSM integration, and pyslang-based workflows. - Reduced build-time friction and increased CI stability through Bazel build improvements and dependency cleanups. - Expanded testing coverage and isolation, leading to fewer flaky tests and more determinism in CI. Technologies and skills demonstrated: - Pyslang integration, Module API expansion, and codegen reuse strategies enabling end-to-end template and instance generation. - FSM-based interface modeling, ap_ctrl port integration, and robust port lifecycle management. - Bazel-based build configuration, VitIS-mode handling, and improved output handling. - Code quality discipline: clang-format quotas, refactoring, and test architectural improvements. Business value: - Faster iteration cycles for hardware-software co-design with TAP-accelerated pipelines. - More reliable builds and tests reduce downtime and QA overhead while enabling broader experimentation with module APIs and pyslang-based tooling.
March 2025
50 Commits • 17 Features
Mar 1, 2025March 2025 (rapidstream-tapa): Key platform improvements and reliability enhancements across Tapac, libtapa, and the build/test pipeline. The month delivered substantive refactors, new tooling integrations, and CI/quality improvements that collectively boost maintainability, hardware-software co-design reliability, and time-to-value for customers relying on TAP-accelerated flows. Key features delivered: - Tapac: Core port handling refactor and FSM integration: added FSM ap_ctrl ports, consolidated add_ports usage in add_m_axi, and streamlined port removal to simplify codegen and port lifecycle management. (Commits include: cdc7ba33, 958fc60b, 1470f4a) - Tapac: PyslangRewriter and pyslang-powered Module API: introduced PyslangRewriter, and expanded Module API with add_instance/del_instances/add_rs_pragmas/add_logics, template generation, and pyslang-enabled defaults for streamlined codegen. (Commits include: b978eb90, d52f213d, d5a77a5f, 7ed03f1e, 06d7ef38, e93abfd2, a8a6c05b, 3c591a5c, 957b5020, 201f2be7) - IO/Module constructs with pyslang: added IOPort, Module.ports, Module.signals, Module.params support via pyslang, enabling richer hardware interface modeling. (Commits include: 69d8ac94, 0a9e6912, bcaacd79, 4d0b2554) - Build and tooling improvements: Bazel build enhancements to treat output_file as attr.output, explicitly set work_dir, and propagate vitis_mode to tapa_xo; CI/workflow cleanup to remove iverilog dependency and adjust wrangler R2 CLI. (Commits include: bb88133d, 98585617, d96c3f64, d0a348b30, 39d80499, fd0c9b11) - Code quality, tests, and refactors: labelling and pruning of unused code, test coverage expansions (e.g., labeling PE loops, pragma deletion; do-not-share-project-dir test fixes), and broader refactors to reuse codegen and improve module/item management. (Commits include: 8c14a974, 792fa26a, 4c695b5c, 8f12eb8c, 6328ba1a, 0a3155f8) Major bugs fixed: - Tapac argument and port handling fixes: skip nonexistent arguments, fix repeated port_names access, address missing ports with --no-vitis-mode, and ensure FSM pragma initialization occurs. (Commits include: 4c7e5bb5, 372738db, 1e2fa5ec, 67bc4d80) - Libtapa: Correct argument access order to preserve sequencing reliability. (Commit: c1e53771) - LLVM build hygiene: fix -Wno-unused-variable handling for cleaner warnings. (Commit: deecd151) - Test isolation and memory layout fixes: ensure test(stream-top) does not share project dir; fix host memory layout in cannon tests; RNG usage and test variants updated. (Commits: d9910a99, 5b674957, f691abdd) - Tapac teardown and parameter parsing cleanup: ensure del_port behavior does not delete header ports and remove problematic parameter statements via pyslang. (Commits: 02346273, 6d458216) - CI/docs cleanup: remove iverilog as dependency and align docs/CLI accordingly. (Commits: d0a348b3, 39d80499, fd0c9b11) Overall impact and accomplishments: - Significantly improved Tapac reliability and flexibility for hardware-software co-design, with safer port management, FSM integration, and pyslang-based workflows. - Reduced build-time friction and increased CI stability through Bazel build improvements and dependency cleanups. - Expanded testing coverage and isolation, leading to fewer flaky tests and more determinism in CI. Technologies and skills demonstrated: - Pyslang integration, Module API expansion, and codegen reuse strategies enabling end-to-end template and instance generation. - FSM-based interface modeling, ap_ctrl port integration, and robust port lifecycle management. - Bazel-based build configuration, VitIS-mode handling, and improved output handling. - Code quality discipline: clang-format quotas, refactoring, and test architectural improvements. Business value: - Faster iteration cycles for hardware-software co-design with TAP-accelerated pipelines. - More reliable builds and tests reduce downtime and QA overhead while enabling broader experimentation with module APIs and pyslang-based tooling.
February 2025
15 Commits • 4 Features
Feb 1, 2025February 2025 monthly summary for rapidstream-org/rapidstream-tapa: Key features delivered: - TapaFastCosimDevice resume from post-simulation state: enables resuming a cosim run by launching as a no-op when FLAGS_xosim_resume_from_post_sim is true, with test infrastructure to verify resume behavior. - Module introspection: pyslang-based module name resolution exposed via a new _name_pyslang property parsed from the syntax tree; activated when Options.enable_pyslang is enabled. - Xilinx synthesis reporting and synth-util integration: added post-synthesis resource/utilization reporting utilities and the --enable-synth-util flag, plus tests for the feature. - UniqueAttrs utility: added UniqueAttrs in tapa.common to manage one-time attributes with unit tests validating initialization, access, and duplicate handling. - TAPA tool modernization and cleanup: codebase simplifications including removal of OrderedDict usage, cleanup of unused constants/functions, and merging link into synth for a simpler CLI. Major bugs fixed: - Docker image base fix for Rocky Linux 9: ensures the correct Rocky Linux 9 image is pulled during builds (commit 1bcc838f3d3b054de415a196b125355274c0308b). - TAPA tool modernization cleanup: multiple refactors to remove deprecated/unused elements (OrderedDict, BUILTIN_INSTANCES, ctrl_instance_name) and merge link into synth (commits c41a0e0f9e0a1a2be2bee5f4399c7f012229c26f, cc51c70159aad06a8a44ebf61ba31fb38acadf00, 38e3cca88a4100b4efaedf0871afb9a1649f81f9, 8bdf0b05966a218ec174f7061f25e5a51f19785a). - Docs and typing maintenance: pinning Sphinx to address Breathe compatibility and improvements to typing (commits d26ae41cbaf72b34773363ea21ab7a756b63e8fc, e7b2e676a13384c8042ad6df909f702d6fe55069). Overall impact and accomplishments: - Strengthened developer experience and reliability of the TAPA toolchain through resume capabilities, enhanced module visibility, and post-synthesis reporting. - Improved CI stability and build reproducibility via Docker image fix and codebase cleanup, reducing maintenance burden. - Introduced safer attribute handling with UniqueAttrs, improving correctness in one-time attribute usage. Technologies/skills demonstrated: - Python, pyslang integration, and syntax-tree parsing for dynamic module naming. - Post-simulation tooling for cosimulation workflows and test infrastructure. - Xilinx RTL synthesis reporting and test automation for synthesis-util features. - Codebase modernization (refactoring for maintainability), containerized builds (Docker), and docs/typing maintenance (Sphinx, type hints).
15 Commits • 4 Features
Feb 1, 2025February 2025 monthly summary for rapidstream-org/rapidstream-tapa: Key features delivered: - TapaFastCosimDevice resume from post-simulation state: enables resuming a cosim run by launching as a no-op when FLAGS_xosim_resume_from_post_sim is true, with test infrastructure to verify resume behavior. - Module introspection: pyslang-based module name resolution exposed via a new _name_pyslang property parsed from the syntax tree; activated when Options.enable_pyslang is enabled. - Xilinx synthesis reporting and synth-util integration: added post-synthesis resource/utilization reporting utilities and the --enable-synth-util flag, plus tests for the feature. - UniqueAttrs utility: added UniqueAttrs in tapa.common to manage one-time attributes with unit tests validating initialization, access, and duplicate handling. - TAPA tool modernization and cleanup: codebase simplifications including removal of OrderedDict usage, cleanup of unused constants/functions, and merging link into synth for a simpler CLI. Major bugs fixed: - Docker image base fix for Rocky Linux 9: ensures the correct Rocky Linux 9 image is pulled during builds (commit 1bcc838f3d3b054de415a196b125355274c0308b). - TAPA tool modernization cleanup: multiple refactors to remove deprecated/unused elements (OrderedDict, BUILTIN_INSTANCES, ctrl_instance_name) and merge link into synth (commits c41a0e0f9e0a1a2be2bee5f4399c7f012229c26f, cc51c70159aad06a8a44ebf61ba31fb38acadf00, 38e3cca88a4100b4efaedf0871afb9a1649f81f9, 8bdf0b05966a218ec174f7061f25e5a51f19785a). - Docs and typing maintenance: pinning Sphinx to address Breathe compatibility and improvements to typing (commits d26ae41cbaf72b34773363ea21ab7a756b63e8fc, e7b2e676a13384c8042ad6df909f702d6fe55069). Overall impact and accomplishments: - Strengthened developer experience and reliability of the TAPA toolchain through resume capabilities, enhanced module visibility, and post-synthesis reporting. - Improved CI stability and build reproducibility via Docker image fix and codebase cleanup, reducing maintenance burden. - Introduced safer attribute handling with UniqueAttrs, improving correctness in one-time attribute usage. Technologies/skills demonstrated: - Python, pyslang integration, and syntax-tree parsing for dynamic module naming. - Post-simulation tooling for cosimulation workflows and test infrastructure. - Xilinx RTL synthesis reporting and test automation for synthesis-util features. - Codebase modernization (refactoring for maintainability), containerized builds (Docker), and docs/typing maintenance (Sphinx, type hints).
February 2025
January 2025
33 Commits • 16 Features
Jan 1, 2025January 2025 (2025-01) highlights for rapidstream-tapa focused on stability, test automation, and tooling across TAPAC, cosimulation, and CI pipelines. Delivered key TAPAC cleanup refactor (removing unused countdown and Pipeline level) and graph tests improvements with debugging aids; enhanced reproducibility and test instrumentation through XO packaging and pyslang integration. Fixed critical reliability issues including graceful bailout when vendor GCC is not found and improved cosimulation cleanup to avoid premature exits, plus longer cosimulation timeout to reduce flakiness. Strengthened CI/build hygiene with upstream buildifier, configurable tool paths, and pre-run cleanup of stale containers, reducing flaky CI runs. Broadened hardware validation and reporting through Verilog Xilinx tests and a tapa-visualizer transition, while keeping a focus on business value by accelerating release readiness and reducing maintenance overhead.
January 2025
33 Commits • 16 Features
Jan 1, 2025January 2025 (2025-01) highlights for rapidstream-tapa focused on stability, test automation, and tooling across TAPAC, cosimulation, and CI pipelines. Delivered key TAPAC cleanup refactor (removing unused countdown and Pipeline level) and graph tests improvements with debugging aids; enhanced reproducibility and test instrumentation through XO packaging and pyslang integration. Fixed critical reliability issues including graceful bailout when vendor GCC is not found and improved cosimulation cleanup to avoid premature exits, plus longer cosimulation timeout to reduce flakiness. Strengthened CI/build hygiene with upstream buildifier, configurable tool paths, and pre-run cleanup of stale containers, reducing flaky CI runs. Broadened hardware validation and reporting through Verilog Xilinx tests and a tapa-visualizer transition, while keeping a focus on business value by accelerating release readiness and reducing maintenance overhead.
December 2024
20 Commits • 3 Features
Dec 1, 2024December 2024 monthly summary for rapidstream-tapa: Focused on stabilizing the build system, strengthening toolchain integration, and improving CI/test reliability, with targeted code cleanups to boost maintainability. Delivered three feature clusters that drive developer velocity and product reliability: (1) Build System Stabilization and Toolchain Integration, consolidating build configuration, toolchain management, and packaging to improve developer experience and reliability, with robust integration for TAPA, ASAN, and the LLVM toolchain and several Bazel packaging improvements; (2) CI/Testing Reliability Enhancements, extending test timeouts, refining staging/build triggers, and eliminating CI races (notably in pre-commit buildifier), resulting in more predictable test runs and faster feedback; (3) Code Cleanup and Refactoring, removing dead code and simplifying interfaces across Verilog Xilinx modules, core, and module classes to reduce bugs and maintenance costs. Major fixes included addressing race conditions in pre-commit buildifier, extending cannon-xosim timeout, and tightening CI triggers to avoid unnecessary full builds on development branches.
20 Commits • 3 Features
Dec 1, 2024December 2024 monthly summary for rapidstream-tapa: Focused on stabilizing the build system, strengthening toolchain integration, and improving CI/test reliability, with targeted code cleanups to boost maintainability. Delivered three feature clusters that drive developer velocity and product reliability: (1) Build System Stabilization and Toolchain Integration, consolidating build configuration, toolchain management, and packaging to improve developer experience and reliability, with robust integration for TAPA, ASAN, and the LLVM toolchain and several Bazel packaging improvements; (2) CI/Testing Reliability Enhancements, extending test timeouts, refining staging/build triggers, and eliminating CI races (notably in pre-commit buildifier), resulting in more predictable test runs and faster feedback; (3) Code Cleanup and Refactoring, removing dead code and simplifying interfaces across Verilog Xilinx modules, core, and module classes to reduce bugs and maintenance costs. Major fixes included addressing race conditions in pre-commit buildifier, extending cannon-xosim timeout, and tightening CI triggers to avoid unnecessary full builds on development branches.
December 2024
November 2024
29 Commits • 8 Features
Nov 1, 2024November 2024 saw substantial streaming and memory-management improvements in FRt and LibTAPA, complemented by API cleanups and build/CI enhancements. Key features delivered include SharedMemoryStream integration for FRt; internal API refactors with StreamArg (renaming StreamWrapper, making it opaque), internalization of idx, and delaying xosim IO buffering; cosim streaming across FRt and LibTAPA; stringify enhancements for FRt and elem_t stringify customization in LibTAPA; and the addition of the fpga::Instance::IsFinished() API for better orchestration. Major bugs fixed include symlink resolution for find_resource in tapac, DPI dynamic library symlink fixes for cosim, and IPC shared-memory handling via shm_open to ensure correct IPC semantics. The work yields higher streaming throughput and reliability, clearer interfaces, improved test coverage for cosim/xosim, and stronger cross-toolchain stability, accelerating silicon exploration. Technologies demonstrated include shared memory IPC, cosim/xosim streaming, API refactors, stringify, and build-system hardening (Nuitka, Debian multilib, HLS parallelism).
November 2024
29 Commits • 8 Features
Nov 1, 2024November 2024 saw substantial streaming and memory-management improvements in FRt and LibTAPA, complemented by API cleanups and build/CI enhancements. Key features delivered include SharedMemoryStream integration for FRt; internal API refactors with StreamArg (renaming StreamWrapper, making it opaque), internalization of idx, and delaying xosim IO buffering; cosim streaming across FRt and LibTAPA; stringify enhancements for FRt and elem_t stringify customization in LibTAPA; and the addition of the fpga::Instance::IsFinished() API for better orchestration. Major bugs fixed include symlink resolution for find_resource in tapac, DPI dynamic library symlink fixes for cosim, and IPC shared-memory handling via shm_open to ensure correct IPC semantics. The work yields higher streaming throughput and reliability, clearer interfaces, improved test coverage for cosim/xosim, and stronger cross-toolchain stability, accelerating silicon exploration. Technologies demonstrated include shared memory IPC, cosim/xosim streaming, API refactors, stringify, and build-system hardening (Nuitka, Debian multilib, HLS parallelism).
Activity
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Quality Metrics
Correctness89.6%
Maintainability90.0%
Architecture86.8%
Performance82.4%
AI Usage21.4%
Skills & Technologies
Programming Languages
BATSBashBazelCC++DockerfileMarkdownPythonRSTShell
Technical Skills
AST ManipulationAST ParsingBackend DevelopmentBazelBazel Build SystemBug FixBuild AutomationBuild SystemBuild System ConfigurationBuild System IntegrationBuild System ManagementBuild System RefactoringBuild SystemsBuild Systems (Bazel)Build Tools
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