Developed and integrated Frame Configuration Multiplexing Modules within the YosysHQ/yosys repository, focusing on enhancing frame-based configuration capabilities for FPGA design workflows. This work introduced configurable multiplexing paths, allowing for greater design flexibility and improved reuse across hardware mapping processes. Using Verilog and hardware design principles, the implementation provided a foundation for more robust configuration-driven synthesis and verification. The approach emphasized modularity and testability, supporting broader integration with existing synthesis tools. Over the course of the month, the contribution centered on expanding the configurability of frame management, laying groundwork for future enhancements in both design coverage and verification strategies.