Month: 2026-03 Summary for OpenXiangShan projects: Key features delivered (OpenXiangShan/difftest): - DifftestClockGate: Added conditional compilation gated by CONFIG_DIFFTEST_CLOCKGATE to improve modularity and configurability of simulations. Commit 5e6f2308. - Difftest macro guards robustness: Fixed inclusion guards in DifftestMacros.svh to ensure proper inclusion based on defined conditions, preventing miscompilations. Commit 63cd46e1. - Difftest signal handling and cleanup: Introduced signal handlers to ensure proper cleanup and reporting on interruptions or crashes, enhancing robustness of test runs. Commit 50cf9f13. - DiffTest documentation and developer guide: Added guidance for developers and AI agents to interact with the DiffTest codebase, reducing errors and improving collaboration. Commit 33dedfaa. - Performance counters: monitoring and runtime tick configuration: Implement performance counter dumping/cleanup at intervals and introduce a runtime parameter for tick cycles to configure performance counters without recompilation. Commits 5a4b9fee and 8085a5a8. - Cosim script enhancements for FPGA simulations: Added a new cosim.sh script (replacing ci.sh) to allow passing workload and diff parameters for FPGA simulations, with optional waveform support for flexible testing scenarios. Commit 2bc89d85. - Nightly regression workflow for XiangShan: Implement a nightly regression testing workflow focusing on PLDM and FPGA simulations, including environment setup, Verilog generation, and Linux/microbench workloads. Commit 89d27d27. Key features delivered (OpenXiangShan/XiangShan): - Dynamic SimAXIMem sizing via --sim-mem-size: Enables configuring SimAXIMem size dynamically through the --sim-mem-size argument, allowing users to specify memory size in GB. This updates Makefile, argument parser, and simulation parameters to support the new functionality. Commit bc4bacba. - Remove legacy DEBUG_ARGS for FPGA differential testing: Removes legacy DEBUG_ARGS to clean up build configurations, reducing potential confusion and improving maintainability for FPGA differential testing workflows. Commit 43dadb39. Major bugs fixed: - Difftest macro guards and build configurations cleaned up to prevent miscompilations; legacy DEBUG_ARGS removed for FPGA differential testing to reduce confusion. Overall impact and accomplishments: - Strengthened verification reliability, configurability, and automation across Difftest and XiangShan flows, enabling safer experiments, faster feedback, and easier onboarding for contributors and AI agents. Improved resource flexibility and reduced maintenance burden through runtime parameterization and updated tooling. Technologies/skills demonstrated: - SystemVerilog macro guards, conditional compilation, signal handling, runtime parameterization, shell scripting for FPGA cosim, and CI/testing workflow orchestration. Business value: - More reliable test outcomes, flexible simulation environments, and accelerated development cycles with improved developer guidance and automation.

February 2026 OpenXiangShan/difftest monthly summary focused on delivering robust FPGA timing and verification improvements, expanding Verilator waveform support, improving performance data reliability, and hardening batch/query handling. These efforts enhanced design timing control, debugging capabilities, and test accuracy across FPGA and Verilator simulations, delivering tangible business value through faster verification cycles and more reliable metrics.

January 2026 performance summary: Delivered substantial reliability and mapping improvements across OpenXiangShan's Difftest and XiangShan repositories, with targeted delta processing enhancements, clearer Difftest signal naming, and expanded CI/test infrastructure. These efforts yielded higher data integrity, faster feedback loops, and more maintainable test harnesses, enabling safer releases and more efficient hardware verification. Key feature deliveries and reliability improvements across repos: - OpenXiangShan/difftest: • Delta Processing Reliability and Robustness: validated DeltaInfo, invalidated Delta outputs when updates are cleared, enlarged Delta queue depth to 4, transferred DeltaInfo only when lastPending, and added PhyReg filtering by Rat and Instr wpdest. • Difftest Framework Reliability and Mapping: explicit signal naming for Difftest sources and explicit phy->arch register mapping with dedicated archTarget and ratTarget. • SQLite Data Representation Enhancement: added script to convert integer columns to hexadecimal format for better data representation. • CI and Test Infrastructure Enhancements: added NO_FINISH_AFTER_WORKLOAD toggle, improved load/squash checks, support for emulation with Squash, and robust CI cleanup/failure handling. • FPGA Simulation Clocking and Modularity: decoupled clockgate from fpga_sim and later reverted gpu gateway to gated clock to stabilize FPGA simulations pending pipeline refactor. • FPGA CI/Regression hygiene: improved nightly tracking and default-branch handling to stabilize FPGA-related tests. - OpenXiangShan/XiangShan: • Difftest Framework Enhancements: introduced top-prefix configuration and an object-oriented refactor of the Difftest C++ code, plus an updated submodule reference to keep integrations current. • Xiangshan Test: Fix forkArgs reference to xiangshan.forkArgs to ensure correct argument handling during test execution.

December 2025 performance summary: Focused on delivering business-value features, stabilizing testing and release workflows, and enabling scalable verification across OpenXiangShan/difftest, XiangShan, and CoupledL2. Highlights include hardware-area improvements from multi-cycle Delta transmission, streamlined Top IO wiring with explicit naming and automatic clock/reset handling, and expanded testing tooling that enables smoother multi-core verification and automated interface generation. These efforts reduce risk, accelerate FPGA release readiness, and provide a solid foundation for future multi-core deployments and configurable platforms.

November 2025 monthly summary: Delivered substantive Difftest and verification improvements across the XiangShan ecosystem, emphasizing documentation, interface modernization, data handling, and maintainability. These efforts improved verification accuracy, reduced hardware/software integration effort, and accelerated CI/debug cycles.

October 2025: OpenXiangShan/difftest delivered two high-impact changes that improve test control and build reliability. Implemented partial-name based exclusion for DifftestBundles and refactored DPI-C import scope in MemRWHelper to prevent conflicts. These changes reduce maintenance overhead, speed up test filtering, and tighten build isolation across multi-instance configurations.

September 2025 monthly summary for OpenXiangShan/difftest focused on delivering hardware-test reliability improvements and workflow efficiency. Key features were introduced to enable CPU-specific diff checks, real-time test visibility, and streamlined FPGA build/emulation workflows, complemented by data processing optimizations in the test/query stack. The work reduces debug cycles, improves test coverage accuracy across CPU types, and strengthens the end-to-end hardware-software validation pipeline.

July 2025 was focused on stability, correctness, and maintainability for OpenXiangShan/difftest. The month delivered targeted bug fixes across FPGA synthesis gating, log file naming, and gsim memory behavior, reducing build-risk and improving runtime reliability. No new user-facing features were introduced this month; the work targeted core reliability to accelerate future feature delivery.

June 2025 monthly summary for OpenXiangShan/difftest focusing on delivering software-simulated FPGA-host interactions, cross-simulator compatibility, and build/synthesis reliability. Key improvements enabled earlier-stage hardware/software integration, improved test coverage, and stabilized the build and synthesis path for production-like validation.

May 2025 monthly focus centered on strengthening hardware-in-the-loop validation and cross-environment consistency for OpenXiangShan/difftest. Delivered FPGA IO exposure via finishFPGA integrated into the batch processing path, and stabilized cross-environment testing by refactoring difftest logic to reuse common nstep across emu, simv, and FPGA, reducing duplication and improving simulation reliability.

April 2025 performance-driven delivery: improved simulation stability, non-blocking DPI-C integration, and enhanced hardware emulation tooling/docs to accelerate development and testing.

March 2025 monthly summary for OpenXiangShan repository. Delivered a refactored batch processing system and optimized delta data transmission, with a focus on performance, scalability, and reliability across multi-core configurations.

Month: 2025-02 Overview: A performance-focused sprint across OpenXiangShan repositories delivering architecture improvements, data-readiness enhancements, and instrumentation for faster iteration, better diagnostics, and scalable simulations. The following features and optimizations were completed with traceable commits, delivering tangible business value in efficiency, reliability, and engineering velocity. Key features delivered: - Preprocessing module refactor and single-core optimization: moved preprocessing to a dedicated Preprocess.scala module and skipped loadEvent data for single-core configurations to reduce unnecessary work. Commits: 0d4f3e9e13310a5950761af8227f8aa52adbc92a; 153ee3781851d0de0b9e42d925edc0b7579532c2. - DPIC data querying and granular performance metrics: added SQLite-backed DPIC query support with new build targets, plus detailed per-DiffState counters in batch mode for better observability. Commits: 199cfeeee193d1fa9f6dc91a33dc13bf95d24af5; d4231867c0de3c52aeda80967f55d6f2b0e101f3. - Batch processing optimization and FPGA-specific gate reduction: introduced a two-stage collector, disabled batch data split strategy for FPGA to reduce gates, and renamed BatchInterval to BatchStep for clarity. Commits: b3dabd511cf6c22aae3f0e7d28c8acda696e68d3; 560e044d76be8cf60e29ff4a6e81e8be6f99f1a1; b537f528bbb9e400b9d0da8756219a5f6d107be9. - Global simulation performance optimizations: reduced gate usage by mapping fwrite to TB_IMPORT in LogPerfEndpoint and enabled -O3 optimization for PLDM C++ builds. Commits: f8746f082b2731e29b5c0cb735e2fe96b45dd7de; 3461e9758a4774234f81c1258f1eda2171a27dad. - Instrumentation and debugging enhancements: improved logging for complex data through WireInit-based probing in LogUtils; XSDebug enhancements to collect missing debug information and probe sub-accessed data. Commits: 5e9df6433098d626c05f927b3539d886e98c5bb6; 1eb8dd224d63ba7d4afa63695f72d8230e150d37. Major bugs fixed: - Fix(LogUtils): support probe subaccess data (#100), enabling robust logging for dynamic indexing scenarios and making subaccess data more reliably observable in diagnostics. Overall impact and accomplishments: - Performance: substantial improvements in simulation throughput and data-query responsiveness, with reduced gate counts on FPGA targets and more efficient batch processing. - Observability: richer metrics and logging instrumentation enabling quicker diagnosis and validation of changes across preprocessing, DPIC data paths, and debugging tooling. - Velocity: clearer module boundaries (Preprocess.scala) and better build-time optimizations (SQL-backed queries, -O3) accelerating development cycles. Technologies/skills demonstrated: - Scala module design and refactor (Preprocess.scala) and clarity improvements in StepInfo naming (BatchStep). - Data engineering: SQLite-backed queries and per-state performance counters. - Hardware-oriented optimization: batch data routing, gate count awareness for FPGA targets. - Performance engineering: -O3 compiler optimizations and performance-oriented mappings (LogPerfEndpoint). - Instrumentation and debugging: advanced logging with WireInit probing and enhanced XSDebug debugging for dynamic indexing.

January 2025: Cross-repo delivery of a robust Difftest-enabled verification flow and configurable performance controls across OpenXiangShan/difftest, OpenXiangShan/XiangShan, OpenXiangShan-Nanhu/Nanhu-V5, and OpenXiangShan/Utility. Key work stabilized the Difftest integration, improved gateway/interface management, and introduced granular performance instrumentation. The investments yielded a more reliable verification loop, faster feedback during FPGA simulations, and a clearer mapping of business value to engineering output.

Month 2024-12 performance-focused contributions across XiangShan, NEMU, and Utility repositories, delivering feature enhancements, build configurability, centralized monitoring, and stability improvements.

2024-11 Monthly summary for OpenXiangShan/difftest: Key reliability and maintainability improvements through bug fix and replay feature enhancements. This period focused on stabilizing gsim integration and improving test replay accuracy to improve debugging and CI reliability.

In 2024-10, delivered significant improvements to OpenXiangShan/difftest. Implemented correctness fixes for squashed commits by updating ArchRegState to apply only on commit or event and adding an updateDependency field to relevant state classes (commit 85823ebb1c6f58d55b589e2ccbdc4e0737690d1f). Also integrated GSIM with the Verilator-based workflow, introducing a GSIM build path and Makefile target to enable GSIM execution (commit e95f27baf6f3cb41c00f214e9ce3099f438af9fc). These changes enhance simulation reliability, offer flexible testing between GSIM and Verilator, and accelerate hardware-software co-design validation.