lowRISC/opentitan
Nov 2024 – Nov 2024
1 Month active
Languages Used
CSystemVerilog
Technical Skills
CDPI (Direct Programming Interface)Hardware DesignSystemVerilogVerification
Kip Walker
PROFILE
Kip Walker
Kip enhanced the JTAG DPI subsystem in the lowRISC/opentitan repository, focusing on improving configurability and efficiency for concurrent simulation environments. By introducing plusarg-driven overrides for the TCP port and initial SRST state, Kip enabled multiple simulations to run simultaneously on shared hosts while avoiding reset timing races. The addition of an active control input allowed the jtagdpi module to be selectively enabled or disabled, reducing unnecessary server activity and resource usage. This work demonstrated strong integration of C and SystemVerilog with Direct Programming Interface techniques, addressing verification workflow bottlenecks and increasing determinism and throughput in hardware design verification processes.
Overall Statistics
Feature vs Bugs
100%Features
Repository Contributions
3Total
Bugs
0
Commits
3
Features
1
Lines of code
62
Activity Months1
Your Network
108 people
Work History
November 2024
3 Commits • 1 Features
Nov 1, 2024In November 2024, delivered a targeted enhancement to the JTAG DPI subsystem in lowRISC/opentitan that improves configurability, concurrency, and resource utilization. Implemented plusarg-driven overrides for the jtagdpi TCP port to support concurrent simulations on shared hosts; added a plusarg to specify the initial SRST state to avoid timing races with reset; introduced an active control input to disable jtagdpi when not in use to prevent unnecessary server startup and tick activity. These changes reduce contention in verification environments, increase test throughput, and improve determinism across concurrent runs. Demonstrates strong tooling integration, SystemVerilog DPI usage, and verification workflow improvements.
3 Commits • 1 Features
Nov 1, 2024In November 2024, delivered a targeted enhancement to the JTAG DPI subsystem in lowRISC/opentitan that improves configurability, concurrency, and resource utilization. Implemented plusarg-driven overrides for the jtagdpi TCP port to support concurrent simulations on shared hosts; added a plusarg to specify the initial SRST state to avoid timing races with reset; introduced an active control input to disable jtagdpi when not in use to prevent unnecessary server startup and tick activity. These changes reduce contention in verification environments, increase test throughput, and improve determinism across concurrent runs. Demonstrates strong tooling integration, SystemVerilog DPI usage, and verification workflow improvements.
November 2024
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Quality Metrics
Correctness86.6%
Maintainability86.6%
Architecture86.6%
Performance86.6%
AI Usage20.0%
Skills & Technologies
Programming Languages
CSystemVerilog
Technical Skills
CDPI (Direct Programming Interface)Hardware DesignSystemVerilogVerification
Repositories Contributed To
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