Kai Yu Chen enhanced the vISA parser within the intel/intel-graphics-compiler repository, focusing on support for mixed register and immediate operands in AddrX and AddrY for LSC 2D block load and store instructions. Using C and leveraging expertise in compiler and parser development, Kai introduced new parsing rules that enable more flexible and accurate instruction processing for 2D block operations. This work improved the reliability of parsing and laid the foundation for more robust code generation in graphics workloads. The changes addressed operand variation challenges, ensuring maintainability and traceability while supporting future performance optimizations in the compiler’s parsing infrastructure.