Worked on the YosysHQ/yosys repository to implement automatic lifetime qualifiers for procedural variables in Verilog, addressing the challenge of unnecessary state elements in hardware synthesis. Leveraging C++ programming and compiler design expertise, updated the parsing logic to recognize and correctly handle automatic lifetimes, ensuring procedural variables are managed efficiently within their scopes. Added comprehensive tests to validate the new feature, supporting test-driven development practices and maintaining repository stability. This focused contribution improved hardware generation by producing smaller netlists and faster synthesis cycles, demonstrating a strong grasp of Verilog semantics, hardware description languages, and integration within a large open-source codebase.