OpenXiangShan/XiangShan
Oct 2024 – Sep 2025
11 Months active
Languages Used
ShellYAMLPythonScala
Technical Skills
CI/CDGitHub ActionsShell ScriptingCache Coherence ProtocolsCode CleanupHardware Design
Yanqin Li
PROFILE
Yanqin Li
Liyanqin contributed to the OpenXiangShan/XiangShan repository by engineering robust memory subsystem features and reliability improvements across cache, uncache, and performance testing workflows. Over 11 months, Liyanqin delivered enhancements such as PBMT support in the CHI interconnect, unified performance regression templates, and critical bug fixes in LoadQueueUncache and DCache modules. Their technical approach combined low-level systems programming in Scala and SystemVerilog with CI/CD automation using Shell scripting and GitHub Actions. The work demonstrated deep understanding of hardware-software integration, memory management, and test infrastructure, resulting in more stable, maintainable, and reproducible hardware development and validation processes for the project.
Overall Statistics
Feature vs Bugs
52%Features
Repository Contributions
44Total
Bugs
12
Commits
44
Features
13
Lines of code
2,535
Activity Months11
Your Network
63 people
Work History
September 2025
3 Commits
Sep 1, 2025OpenXiangShan/XiangShan – September 2025: Focused on internal correctness and reliability improvements in the memory subsystem. Implemented targeted fixes to prefetch statistics, counter filter sizing, and LoadUnit behavior during fast replay. No new user-facing features this month; the work materially increases reliability, validation accuracy, and overall system stability, reducing risk in performance benchmarking and regression suites.
3 Commits
Sep 1, 2025OpenXiangShan/XiangShan – September 2025: Focused on internal correctness and reliability improvements in the memory subsystem. Implemented targeted fixes to prefetch statistics, counter filter sizing, and LoadUnit behavior during fast replay. No new user-facing features this month; the work materially increases reliability, validation accuracy, and overall system stability, reducing risk in performance benchmarking and regression suites.
September 2025
August 2025
1 Commits • 1 Features
Aug 1, 2025August 2025 monthly summary for OpenXiangShan/XiangShan: Implemented a reusable performance testing template and version-specific workflows to standardize and accelerate performance regression testing across v2 and v3. Refactored the CI workflow into a template and added dedicated v2/v3 workflows that leverage it, enabling independent testing of different versions and benchmark types. While there were no major bug fixes this month, the work significantly improves test reliability, cross-version comparability, and onboarding for new benchmarks, delivering measurable business value through faster feedback and reduced maintenance.
August 2025
1 Commits • 1 Features
Aug 1, 2025August 2025 monthly summary for OpenXiangShan/XiangShan: Implemented a reusable performance testing template and version-specific workflows to standardize and accelerate performance regression testing across v2 and v3. Refactored the CI workflow into a template and added dedicated v2/v3 workflows that leverage it, enabling independent testing of different versions and benchmark types. While there were no major bug fixes this month, the work significantly improves test reliability, cross-version comparability, and onboarding for new benchmarks, delivering measurable business value through faster feedback and reduced maintenance.
July 2025
1 Commits
Jul 1, 2025July 2025 monthly summary for OpenXiangShan/XiangShan: focused on stabilizing the DCache subsystem and ensuring correctness in memory back type handling; drove reliability improvements with minimal risk changes.
1 Commits
Jul 1, 2025July 2025 monthly summary for OpenXiangShan/XiangShan: focused on stabilizing the DCache subsystem and ensuring correctness in memory back type handling; drove reliability improvements with minimal risk changes.
July 2025
June 2025
2 Commits
Jun 1, 2025June 2025 monthly summary for OpenXiangShan/XiangShan focusing on reliability and test stability. No new user-facing features this month; prioritized critical bug fixes that enhance hardware fault visibility and test determinism. Improvements implemented through targeted code corrections and alignment of difftest timing across store types, strengthening overall robustness for production readiness.
June 2025
2 Commits
Jun 1, 2025June 2025 monthly summary for OpenXiangShan/XiangShan focusing on reliability and test stability. No new user-facing features this month; prioritized critical bug fixes that enhance hardware fault visibility and test determinism. Improvements implemented through targeted code corrections and alignment of difftest timing across store types, strengthening overall robustness for production readiness.
May 2025
5 Commits • 1 Features
May 1, 2025May 2025 monthly summary for OpenXiangShan/XiangShan: focused on reliability of the NC/uncached memory path and timing alignment with NoC latency. Delivered critical NC path fixes and a submodule update to better reflect L2-to-DDR timing, resulting in improved correctness, stability, and performance under difftest and NoC workloads.
5 Commits • 1 Features
May 1, 2025May 2025 monthly summary for OpenXiangShan/XiangShan: focused on reliability of the NC/uncached memory path and timing alignment with NoC latency. Delivered critical NC path fixes and a submodule update to better reflect L2-to-DDR timing, resulting in improved correctness, stability, and performance under difftest and NoC workloads.
May 2025
April 2025
8 Commits • 3 Features
Apr 1, 2025April 2025 Monthly Summary – XiangShan (OpenXiangShan/XiangShan) Overview: Focused effort on memory subsystem stability, prefetcher enablement reliability, and test workflow improvements to deliver measurable business value: higher memory subsystem reliability under load, more accurate performance evaluation, and a streamlined test/reporting process for faster feedback cycles. Key features delivered and major fixes: - Memory Subsystem Correctness and Stability: implemented breadth of fixes across store paths, uncache handling, LSQ arbitration, and related memory pathways to address deadlocks, pointer handling, and data integrity during outstanding requests; optimization to memory handling. Commits include: dd3d70bad8def5b15d6c20ec5888b367b0575198 (fix(Uncache): uncache mm store needs difftest to update goldenmem), 724e3eb416ebe998f14f7c5a930e55e14db05539 (fix(StoreQueue): keep readPtr until slave ack when outstanding), ee92d6ff6844a088fc62700d33aaa5aa2acaf975 (fix(StoreQueue): add nc_req_ack state to avoid duplicated request), 4bbdccbb077840af5e1b65c7138d31af3966f625 (fix(StoreUnit): optimize the code by StoreUnit Code Review), bf62c344af9592cd051303c3c72252abff2946b8 (fix(StoreQueue): strictly ensure deq moves in order), 6172063bf6f277af4a98b6686bd79460b25a2f25 (fix: use a more sensible entry priority of UncacheBuffer). - XiangShan L1 Prefetcher Enablement Logic: refactored enabling logic for SMS and L1 stream prefetchers to ensure prefetching is enabled only when all required control signals are satisfied, improving accuracy and reliability. Commit: 05cc6da9631ca9da7abb3d03ae37e832778a8a0e (fix(prefetch): fix control signals of l1 prefetchers). - Performance Testing Workflow and Reporting Improvements: updated performance testing workflow to support a new file type and improve error reporting; moved .fst wave files to the SPEC directory and added a newline for readability in the test failure summary. Commit: ae2a905865035a6489965fa95b35a048f6add2a0 (ci(perf): fix changed wave file and summary format). Overall impact and accomplishments: - Higher memory subsystem reliability: reduced risk of data corruption and deadlocks under concurrency; more predictable memory request handling. - More accurate performance evaluation: improved test artifacts and failure reporting, enabling faster triage and tuning. - Clearer, maintainable code changes: focused commits with targeted fixes and improvements; easier code review and future enhancements. Technologies and skills demonstrated: - Low-level memory subsystem debugging and stabilization (store queue, uncache paths, LSQ arbitration) - Prefetcher control flow engineering and signal coordination - Test automation improvements and reporting enhancements, with workflow refinements and file organization changes Business value: - Improved system reliability for memory-intensive workloads, reducing downtime and QA cycles. - More actionable performance data leading to faster optimization and capacity planning.
April 2025
8 Commits • 3 Features
Apr 1, 2025April 2025 Monthly Summary – XiangShan (OpenXiangShan/XiangShan) Overview: Focused effort on memory subsystem stability, prefetcher enablement reliability, and test workflow improvements to deliver measurable business value: higher memory subsystem reliability under load, more accurate performance evaluation, and a streamlined test/reporting process for faster feedback cycles. Key features delivered and major fixes: - Memory Subsystem Correctness and Stability: implemented breadth of fixes across store paths, uncache handling, LSQ arbitration, and related memory pathways to address deadlocks, pointer handling, and data integrity during outstanding requests; optimization to memory handling. Commits include: dd3d70bad8def5b15d6c20ec5888b367b0575198 (fix(Uncache): uncache mm store needs difftest to update goldenmem), 724e3eb416ebe998f14f7c5a930e55e14db05539 (fix(StoreQueue): keep readPtr until slave ack when outstanding), ee92d6ff6844a088fc62700d33aaa5aa2acaf975 (fix(StoreQueue): add nc_req_ack state to avoid duplicated request), 4bbdccbb077840af5e1b65c7138d31af3966f625 (fix(StoreUnit): optimize the code by StoreUnit Code Review), bf62c344af9592cd051303c3c72252abff2946b8 (fix(StoreQueue): strictly ensure deq moves in order), 6172063bf6f277af4a98b6686bd79460b25a2f25 (fix: use a more sensible entry priority of UncacheBuffer). - XiangShan L1 Prefetcher Enablement Logic: refactored enabling logic for SMS and L1 stream prefetchers to ensure prefetching is enabled only when all required control signals are satisfied, improving accuracy and reliability. Commit: 05cc6da9631ca9da7abb3d03ae37e832778a8a0e (fix(prefetch): fix control signals of l1 prefetchers). - Performance Testing Workflow and Reporting Improvements: updated performance testing workflow to support a new file type and improve error reporting; moved .fst wave files to the SPEC directory and added a newline for readability in the test failure summary. Commit: ae2a905865035a6489965fa95b35a048f6add2a0 (ci(perf): fix changed wave file and summary format). Overall impact and accomplishments: - Higher memory subsystem reliability: reduced risk of data corruption and deadlocks under concurrency; more predictable memory request handling. - More accurate performance evaluation: improved test artifacts and failure reporting, enabling faster triage and tuning. - Clearer, maintainable code changes: focused commits with targeted fixes and improvements; easier code review and future enhancements. Technologies and skills demonstrated: - Low-level memory subsystem debugging and stabilization (store queue, uncache paths, LSQ arbitration) - Prefetcher control flow engineering and signal coordination - Test automation improvements and reporting enhancements, with workflow refinements and file organization changes Business value: - Improved system reliability for memory-intensive workloads, reducing downtime and QA cycles. - More actionable performance data leading to faster optimization and capacity planning.
March 2025
4 Commits • 1 Features
Mar 1, 2025March 2025 highlights for OpenXiangShan/XiangShan: Delivered critical data-path correctness fixes and significant CI/tooling improvements. Key features delivered: CI and tooling enhancements for reliability and visibility, including longer performance test timeouts and GitHub Actions step summaries, plus ongoing tutorial/script maintenance for smoother runs. Major bugs fixed: core data path correctness fixes—uncache merge now proceeds when possible even if the buffer is full, and the LoadUnit address mux switched to a selection vector to prevent misaddressing. Overall impact: higher reliability of the data path and faster, more actionable test feedback, enabling safer and more efficient integration. Technologies/skills demonstrated: RTL-level debugging and memory-path reasoning, CI/CD optimization, and scripting/refactoring for maintainability.
4 Commits • 1 Features
Mar 1, 2025March 2025 highlights for OpenXiangShan/XiangShan: Delivered critical data-path correctness fixes and significant CI/tooling improvements. Key features delivered: CI and tooling enhancements for reliability and visibility, including longer performance test timeouts and GitHub Actions step summaries, plus ongoing tutorial/script maintenance for smoother runs. Major bugs fixed: core data path correctness fixes—uncache merge now proceeds when possible even if the buffer is full, and the LoadUnit address mux switched to a selection vector to prevent misaddressing. Overall impact: higher reliability of the data path and faster, more actionable test feedback, enabling safer and more efficient integration. Technologies/skills demonstrated: RTL-level debugging and memory-path reasoning, CI/CD optimization, and scripting/refactoring for maintainability.
March 2025
February 2025
7 Commits
Feb 1, 2025February 2025 monthly summary for OpenXiangShan/XiangShan. Focused on hardening the uncached memory path and ensuring correct LDU behavior with TLB interactions, delivering stability improvements in the memory subsystem and reducing risk of data corruption under edge cases. Provided commit-traceable fixes across uncached replay, buffering, flush handling, and misalignment scenarios, plus precise LDU gating on TLB hits.
February 2025
7 Commits
Feb 1, 2025February 2025 monthly summary for OpenXiangShan/XiangShan. Focused on hardening the uncached memory path and ensuring correct LDU behavior with TLB interactions, delivering stability improvements in the memory subsystem and reducing risk of data corruption under edge cases. Provided commit-traceable fixes across uncached replay, buffering, flush handling, and misalignment scenarios, plus precise LDU gating on TLB hits.
January 2025
7 Commits • 3 Features
Jan 1, 2025In January 2025, OpenXiangShan/XiangShan delivered meaningful improvements to the memory subsystem, strengthening correctness, reliability, and performance through targeted bug fixes, memory-protection checks, and submodule-aware integration. The work focused on safer uncached memory paths, alignment with memory region configuration, and improved coordination across L1/L2/L3 caching and the TileLink interface.
7 Commits • 3 Features
Jan 1, 2025In January 2025, OpenXiangShan/XiangShan delivered meaningful improvements to the memory subsystem, strengthening correctness, reliability, and performance through targeted bug fixes, memory-protection checks, and submodule-aware integration. The work focused on safer uncached memory paths, alignment with memory region configuration, and improved coordination across L1/L2/L3 caching and the TileLink interface.
January 2025
December 2024
5 Commits • 3 Features
Dec 1, 2024December 2024 monthly summary for OpenXiangShan/XiangShan. The team delivered core memory-attribute enhancements, expanded validation coverage, and codebase simplifications that collectively improve reliability, performance realism, and maintainability in production workflows. Key features delivered: - PBMT support in CHI interconnect with memory attribute differentiation using memBackTypeMM; submodule updates across CoupledL2 and OpenLLC to enable PBMT in CHI scenes. Commits include 94aa21c6009c2f39c5c5dae9c87260c78887efcc and 519244c70fb0960c61014ad524e609af0918a818. - Svpbmt test coverage in CI: extended CI workloads by appending Svpbmt/rvh_test.bin to test suites to validate Svpbmt behavior. Commit: f346d72749d2a958fafe5aea9f317b64283b416e. - Prefetch refactor and cleanup: removed outdated prefetch code and migrated functionality into mem/prefetch to simplify the codebase. Commit: c092d579936147e86e9bd35883ab10f6d7488f08. Major bugs fixed: - LoadQueueUncache: fix offset allocation logic to ensure canAllocate respects valid offsets when allocating entries from the free list, preventing allocation failures. Commit: 54b55f342d97c8cf80538d141e4d1c7e62dcdbe1. Overall impact and accomplishments: - Strengthened correctness and realism of memory attribute handling (PBMT) in the CHI interconnect, aligning hardware semantics with software models. - Increased confidence in memory subsystem behavior through Svpbmt CI coverage, reducing risk of memory-type regressions. - Codebase simplification through prefetch refactor, lowering maintenance burden and improving future extensibility. - Reliable allocation paths in LoadQueueUncache, reducing run-time allocation failures. Technologies/skills demonstrated: - CHI interconnect design, PBMT integration, and memory attribute modeling. - SVPBMT validation, CI automation, and test coverage strategies. - Codebase refactoring, module coordination (submodules), and memory subsystem ownership. - Debugging and patching of allocation logic within memory caches.
December 2024
5 Commits • 3 Features
Dec 1, 2024December 2024 monthly summary for OpenXiangShan/XiangShan. The team delivered core memory-attribute enhancements, expanded validation coverage, and codebase simplifications that collectively improve reliability, performance realism, and maintainability in production workflows. Key features delivered: - PBMT support in CHI interconnect with memory attribute differentiation using memBackTypeMM; submodule updates across CoupledL2 and OpenLLC to enable PBMT in CHI scenes. Commits include 94aa21c6009c2f39c5c5dae9c87260c78887efcc and 519244c70fb0960c61014ad524e609af0918a818. - Svpbmt test coverage in CI: extended CI workloads by appending Svpbmt/rvh_test.bin to test suites to validate Svpbmt behavior. Commit: f346d72749d2a958fafe5aea9f317b64283b416e. - Prefetch refactor and cleanup: removed outdated prefetch code and migrated functionality into mem/prefetch to simplify the codebase. Commit: c092d579936147e86e9bd35883ab10f6d7488f08. Major bugs fixed: - LoadQueueUncache: fix offset allocation logic to ensure canAllocate respects valid offsets when allocating entries from the free list, preventing allocation failures. Commit: 54b55f342d97c8cf80538d141e4d1c7e62dcdbe1. Overall impact and accomplishments: - Strengthened correctness and realism of memory attribute handling (PBMT) in the CHI interconnect, aligning hardware semantics with software models. - Increased confidence in memory subsystem behavior through Svpbmt CI coverage, reducing risk of memory-type regressions. - Codebase simplification through prefetch refactor, lowering maintenance burden and improving future extensibility. - Reliable allocation paths in LoadQueueUncache, reducing run-time allocation failures. Technologies/skills demonstrated: - CHI interconnect design, PBMT integration, and memory attribute modeling. - SVPBMT validation, CI automation, and test coverage strategies. - Codebase refactoring, module coordination (submodules), and memory subsystem ownership. - Debugging and patching of allocation logic within memory caches.
October 2024
1 Commits • 1 Features
Oct 1, 2024Oct 2024 monthly summary for OpenXiangShan/XiangShan focused on performance and reliability improvements in the CI/CD pipeline and EMU build process. Delivered a biweekly CI/CD cadence, introduced manual runs by a specific commit SHA to ensure controlled, reproducible testing, and implemented EMU build caching to skip rebuilds when a matching EMU already exists. These changes enhance build speed, reproducibility, and developer confidence, with traceability to the committed work (commit 9a0787843269d038fa80430e8a8a1efc9a9c13d5; related notes in PR #3798).
1 Commits • 1 Features
Oct 1, 2024Oct 2024 monthly summary for OpenXiangShan/XiangShan focused on performance and reliability improvements in the CI/CD pipeline and EMU build process. Delivered a biweekly CI/CD cadence, introduced manual runs by a specific commit SHA to ensure controlled, reproducible testing, and implemented EMU build caching to skip rebuilds when a matching EMU already exists. These changes enhance build speed, reproducibility, and developer confidence, with traceability to the committed work (commit 9a0787843269d038fa80430e8a8a1efc9a9c13d5; related notes in PR #3798).
October 2024
Activity
Loading activity data...
Quality Metrics
Correctness87.0%
Maintainability83.6%
Architecture81.6%
Performance75.2%
AI Usage20.0%
Skills & Technologies
Programming Languages
PythonScalaShellYAML
Technical Skills
CI/CDCPU ArchitectureCacheCache CoherenceCache Coherence ProtocolsCache ManagementCode CleanupConfiguration ManagementDebuggingDigital DesignDigital Logic DesignEmbedded SystemsError HandlingGitHub ActionsHardware Design
Repositories Contributed To
Overview of all repositories you've contributed to across your timeline