lowRISC/opentitan
Sep 2025 – Sep 2025
1 Month active
Languages Used
BUILDC++RustStarlark
Technical Skills
Build SystemBuild System ConfigurationBuild SystemsEmbedded SystemsFirmware DevelopmentHardware Design
Loïc Lefort
PROFILE
Loïc Lefort
Worked on the lowRISC/opentitan repository to deliver core Darjeeling enablement, focusing on enhancing the Verilator-based test environment and expanding test harness capabilities. Developed RTL targets and RAM-loading support for Darjeeling IPs, utilizing BUILD and Starlark for robust build system configuration. Improved OTP image generation by updating build scripts to align with the latest Darjeeling OTP map, ensuring data completeness and accuracy. Enabled support for multiple ROM images within the test harness and Verilator simulation, updating related tools and test benches. This work strengthened verification coverage, data integrity, and testing flexibility for future Darjeeling features in embedded systems development.
Overall Statistics
Feature vs Bugs
100%Features
Repository Contributions
5Total
Bugs
0
Commits
5
Features
3
Lines of code
368
Activity Months1
Your Network
128 peopleSame Organization
@rivosinc.com28
Work History
September 2025
5 Commits • 3 Features
Sep 1, 2025September 2025: Delivered core Darjeeling enablement in lowRISC/opentitan, including Verilator-based test environment enhancements, OTP image data improvements, and multi-ROM support in the test harness. These changes improved verification coverage, data integrity, and testing flexibility for future Darjeeling features. Highlights include RTL targets and RAM loading for Verilator, complete OTP images aligned with the Darjeeling OTP map, and support for multiple ROM images (rom0, rom1) in the test harness and tools.
5 Commits • 3 Features
Sep 1, 2025September 2025: Delivered core Darjeeling enablement in lowRISC/opentitan, including Verilator-based test environment enhancements, OTP image data improvements, and multi-ROM support in the test harness. These changes improved verification coverage, data integrity, and testing flexibility for future Darjeeling features. Highlights include RTL targets and RAM loading for Verilator, complete OTP images aligned with the Darjeeling OTP map, and support for multiple ROM images (rom0, rom1) in the test harness and tools.
September 2025
Activity
Loading activity data...
Quality Metrics
Correctness86.0%
Maintainability84.0%
Architecture80.0%
Performance72.0%
AI Usage20.0%
Skills & Technologies
Programming Languages
BUILDC++RustStarlark
Technical Skills
Build SystemBuild System ConfigurationBuild SystemsEmbedded SystemsFirmware DevelopmentHardware DesignHardware SimulationSoftware DevelopmentTooling
Repositories Contributed To
Overview of all repositories you've contributed to across your timeline