Worked on the SpinalHDL/SpinalHDL repository, focusing on core improvements in digital design and hardware description using Scala. Delivered a feature enabling AFix memory initialization from BigDecimal values, converting them to BigInt according to AFix Q resolution and supporting negative values, which enhanced flexibility and correctness in memory modeling. Addressed a critical timing-related bug by refining Timeout and StateDelay calculations, using BigDecimal arithmetic and rounding to the nearest cycle to minimize off-by-one errors. These changes improved simulation fidelity and reliability for timing-sensitive HDL generation, demonstrating careful attention to numerical precision and robust handling of hardware modeling requirements.