Worked on advancing RISC-V architecture support by implementing the Zlasr and Zalasr extensions across espressif/llvm-project and riscv/riscv-isa-manual repositories. Developed backend logic in C++ and LLVM IR to correctly lower atomic load-acquire and store-release operations, ensuring compliance with Zlasr semantics and memory ordering models such as TSO. Enhanced instruction selection and expanded test coverage to validate atomic operation correctness. Contributed to the RISC-V ISA specification by integrating Zalasr, refining synchronization capabilities, and updating Asciidoc documentation for clarity. The work demonstrated depth in compiler development, low-level optimization, and embedded systems, focusing on robust, standards-aligned feature delivery.