Worked on the chipsalliance/chisel repository to optimize performance and reliability in hardware description workflows. Focused on improving the efficiency of the containsProbe computation for aggregates by introducing a caching mechanism using a new lazy val, elementsContainProbe, within AggregateImpl and VecImpl. This approach reduced redundant calculations and enhanced runtime performance. Comprehensive unit tests were developed to ensure correctness across various aggregate and probe scenarios, strengthening test coverage and code robustness. The work was implemented using Scala and leveraged expertise in Hardware Description Language and testing methodologies, reflecting a targeted and methodical approach to advancing core infrastructure within the project.