Worked on the golang/arch repository to address a correctness issue in the representation of RISCV FENCE IOPW instructions. Focused on aligning the memOrder bit order with the official RISCV manual, the solution involved a targeted bug fix that improved the accuracy of instruction string representations. The patch was implemented in Go and demonstrated skills in low-level and system programming, with careful attention to hardware specification details. The change underwent thorough code review and continuous integration validation, reducing the risk of misinterpretation in architectural modeling and tooling while enhancing the maintainability and reliability of the arch package for future updates.