lowRISC/opentitan
Apr 2026 – May 2026
2 Months active
Languages Used
SystemVerilogVerilog
Technical Skills
FPGA designFPGA developmentI2C protocolSystemVerilogdigital designhardware design
Neil Webb
PROFILE
Neil Webb
Contributed to the lowRISC/opentitan hardware repository by enhancing cross-clock-domain reliability in FPGA-based I2C and asynchronous FIFO data paths. Focused on clock-domain crossing hardening, the work involved synchronizing I2C signals and stabilizing shadow-register and error paths using SystemVerilog and Verilog. Addressed combinational logic issues in finite state machines to improve synthesis safety and verification. Delivered DFT-compliant fixes for asynchronous FIFO modules, ensuring reliable data transfer and improved testability across domains. These efforts strengthened data integrity and maintainability in multi-top SoC deployments, demonstrating depth in FPGA development, digital design, and hardware design within a complex open-source hardware environment.
Overall Statistics
Feature vs Bugs
33%Features
Repository Contributions
6Total
Bugs
2
Commits
6
Features
1
Lines of code
2,882,857
Activity Months2
Your Network
136 peopleWork History
May 2026
2 Commits
May 1, 2026Concise monthly delivery for lowRISC/opentitan focused on stabilizing the asynchronous FIFO path for cross-domain data movement. Implemented DFT-compliant fixes in prim_fifo_async_simple used by rv_dm and lc_ctrl, addressing a Design-for-Test violation by making the wready_q signal controllable and aligning the write enable path with the ready signal to ensure proper data write operations. Updated RTL with corrected control signals and improved testability.
2 Commits
May 1, 2026Concise monthly delivery for lowRISC/opentitan focused on stabilizing the asynchronous FIFO path for cross-domain data movement. Implemented DFT-compliant fixes in prim_fifo_async_simple used by rv_dm and lc_ctrl, addressing a Design-for-Test violation by making the wready_q signal controllable and aligning the write enable path with the ready signal to ensure proper data write operations. Updated RTL with corrected control signals and improved testability.
May 2026
April 2026
4 Commits • 1 Features
Apr 1, 2026April 2026 focused on reinforcing cross-clock-domain reliability in the opentitan hardware design, delivering clock-domain crossing hardening for the I2C IP, stabilizing shadow-register paths, and tightening CDC-related logic in critical fault paths. The work improved data integrity across domains, reduced risk of timing-related errors, and enhanced maintainability of multi-top deployments. A targeted bug fix eliminated CDC-related combinational logic flags in the prim_sync_reqack FSM, contributing to safer synthesis and easier verification. Collectively, these changes improve reliability for I2C communications, JTAG/CPU request paths, and cross-domain signaling across multiple SoC tops.
April 2026
4 Commits • 1 Features
Apr 1, 2026April 2026 focused on reinforcing cross-clock-domain reliability in the opentitan hardware design, delivering clock-domain crossing hardening for the I2C IP, stabilizing shadow-register paths, and tightening CDC-related logic in critical fault paths. The work improved data integrity across domains, reduced risk of timing-related errors, and enhanced maintainability of multi-top deployments. A targeted bug fix eliminated CDC-related combinational logic flags in the prim_sync_reqack FSM, contributing to safer synthesis and easier verification. Collectively, these changes improve reliability for I2C communications, JTAG/CPU request paths, and cross-domain signaling across multiple SoC tops.
Activity
Loading activity data...
Quality Metrics
Correctness96.6%
Maintainability90.0%
Architecture96.6%
Performance90.0%
AI Usage20.0%
Skills & Technologies
Programming Languages
SystemVerilogVerilog
Technical Skills
FPGA designFPGA developmentI2C protocolSystemVerilogdigital designhardware design
Repositories Contributed To
Overview of all repositories you've contributed to across your timeline