intel/intel-graphics-compiler
Sep 2024 – Apr 2026
19 Months active
Languages Used
C++LLVM IROpenCLCOpenCL CYAMLCLLLVM
Technical Skills
C++ developmentcompiler optimizationC++ programmingperformance tuningCode AnalysisCompiler Development
Kwasniewski, Patryk
PROFILE
Kwasniewski, Patryk
Patryk Kwasniewski developed advanced compiler optimizations and reliability improvements for the intel/intel-graphics-compiler over 19 months, focusing on OpenCL and SPIR-V workloads. He engineered features such as vectorization, memory footprint reduction, and hardware-accelerated intrinsics, using C++ and LLVM to deliver platform-specific enhancements. Patryk’s work included payload header compression, kernel argument pruning, and cache control extensions, all aimed at improving throughput and code generation efficiency. He addressed correctness in memory analysis and optimization passes, balancing performance gains with stability through careful feature flagging and targeted rollbacks. His contributions demonstrated deep understanding of low-level programming and robust, maintainable engineering practices.
Overall Statistics
Feature vs Bugs
70%Features
Repository Contributions
81Total
Bugs
12
Commits
81
Features
28
Lines of code
16,378
Activity Months19
Your Network
2213 peopleSame Organization
@intel.com2082
Work History
April 2026
1 Commits • 1 Features
Apr 1, 2026April 2026 focused on enhancing memory fence operations and cache control within the Intel Graphics Compiler to improve memory throughput and predictability. Implemented an enhanced memory fence with extended cache control options, broadened the L1 eviction logic, and added regression tests to validate the extended behavior. The changes primarily modify emitMemoryFence to support extended cache controls and expand test coverage.
1 Commits • 1 Features
Apr 1, 2026April 2026 focused on enhancing memory fence operations and cache control within the Intel Graphics Compiler to improve memory throughput and predictability. Implemented an enhanced memory fence with extended cache control options, broadened the L1 eviction logic, and added regression tests to validate the extended behavior. The changes primarily modify emitMemoryFence to support extended cache controls and expand test coverage.
April 2026
March 2026
2 Commits • 1 Features
Mar 1, 2026Month: 2026-03 Repository: intel/intel-graphics-compiler Overview: - Key features delivered: Xe3p Kernel Argument Footprint Reduction. Reduce kernel argument footprint on Xe3p by removing unused implicit local IDs and the private_base implicit kernel argument to optimize memory usage and improve code generation efficiency. This is implemented via the RemoveUnusedIdImplicitLocalIDs pass and post-optimization adjustments. - Major bugs fixed: Correct emission of implicit kernel arguments in Xe3p by ensuring private_base is not emitted when alloca is removed by SROA, aligning PrivateMemoryUsageAnalysis with optimization passes and reducing unnecessary kernel surface area. - Overall impact and accomplishments: Reduced memory pressure and kernel argument surface, translating into better memory utilization and potential performance gains for Xe3p workloads; simplified kernel interfaces and improved maintainability of the Xe3p path. - Technologies/skills demonstrated: Compiler IR passes (RemoveUnusedIdImplicitLocalIDs, PrivateMemoryUsageAnalysis), SROA optimization, memory usage modeling, and code generation improvements.
March 2026
2 Commits • 1 Features
Mar 1, 2026Month: 2026-03 Repository: intel/intel-graphics-compiler Overview: - Key features delivered: Xe3p Kernel Argument Footprint Reduction. Reduce kernel argument footprint on Xe3p by removing unused implicit local IDs and the private_base implicit kernel argument to optimize memory usage and improve code generation efficiency. This is implemented via the RemoveUnusedIdImplicitLocalIDs pass and post-optimization adjustments. - Major bugs fixed: Correct emission of implicit kernel arguments in Xe3p by ensuring private_base is not emitted when alloca is removed by SROA, aligning PrivateMemoryUsageAnalysis with optimization passes and reducing unnecessary kernel surface area. - Overall impact and accomplishments: Reduced memory pressure and kernel argument surface, translating into better memory utilization and potential performance gains for Xe3p workloads; simplified kernel interfaces and improved maintainability of the Xe3p path. - Technologies/skills demonstrated: Compiler IR passes (RemoveUnusedIdImplicitLocalIDs, PrivateMemoryUsageAnalysis), SROA optimization, memory usage modeling, and code generation improvements.
February 2026
3 Commits • 1 Features
Feb 1, 2026February 2026 (intel/intel-graphics-compiler): Delivered targeted platform optimizations and ensured cross-generation compatibility. Implemented default enabling of RemoveUnusedIdImplicitLocalIDs on Xe3 and Xe3p to improve code optimization and performance. Reverted the Xe3p change to maintain Xe2 HPG core compatibility, ensuring stability across generations. These changes unlock improved optimization opportunities on Xe3/Xe3p while preserving backward compatibility for Xe2, reducing risk and supporting smoother customer upgrades.
3 Commits • 1 Features
Feb 1, 2026February 2026 (intel/intel-graphics-compiler): Delivered targeted platform optimizations and ensured cross-generation compatibility. Implemented default enabling of RemoveUnusedIdImplicitLocalIDs on Xe3 and Xe3p to improve code optimization and performance. Reverted the Xe3p change to maintain Xe2 HPG core compatibility, ensuring stability across generations. These changes unlock improved optimization opportunities on Xe3/Xe3p while preserving backward compatibility for Xe2, reducing risk and supporting smoother customer upgrades.
February 2026
January 2026
3 Commits • 1 Features
Jan 1, 2026January 2026 monthly summary for intel/intel-graphics-compiler focused on optimizing local ID handling and reducing thread payload. Implemented per-dimension local ID types for OpenCL kernel arguments, added a RemoveUnusedIdImplicitLocalIDs option to prune unused implicit local IDs from the thread payload, and enabled this optimization by default for the Xe2 platform. These changes reduce thread payload size and memory footprint, improve code-generation clarity, and provide Xe2-specific performance benefits in production workloads.
January 2026
3 Commits • 1 Features
Jan 1, 2026January 2026 monthly summary for intel/intel-graphics-compiler focused on optimizing local ID handling and reducing thread payload. Implemented per-dimension local ID types for OpenCL kernel arguments, added a RemoveUnusedIdImplicitLocalIDs option to prune unused implicit local IDs from the thread payload, and enabled this optimization by default for the Xe2 platform. These changes reduce thread payload size and memory footprint, improve code-generation clarity, and provide Xe2-specific performance benefits in production workloads.
November 2025
2 Commits • 1 Features
Nov 1, 2025November 2025: Key performance and reliability improvements in intel-graphics-compiler. Delivered a MAD-based integer multiply optimization pass to transform Y*(X+1) into X*Y+Y, enabling single-instruction MAD paths on MAD-capable hardware; fixed WaveShuffleIndex hoisting to occur after its source within the same basic block and added regression tests. These changes reduce generated code size and instruction count, improve runtime performance on relevant workloads, and strengthen optimization dependency handling. Demonstrated proficiency in IR pattern-based optimizations, control-flow analysis, and regression testing.
2 Commits • 1 Features
Nov 1, 2025November 2025: Key performance and reliability improvements in intel-graphics-compiler. Delivered a MAD-based integer multiply optimization pass to transform Y*(X+1) into X*Y+Y, enabling single-instruction MAD paths on MAD-capable hardware; fixed WaveShuffleIndex hoisting to occur after its source within the same basic block and added regression tests. These changes reduce generated code size and instruction count, improve runtime performance on relevant workloads, and strengthen optimization dependency handling. Demonstrated proficiency in IR pattern-based optimizations, control-flow analysis, and regression testing.
November 2025
October 2025
3 Commits • 1 Features
Oct 1, 2025October 2025 monthly recap for intel/intel-graphics-compiler: Delivered targeted performance optimizations and 64-bit narrowing in codegen, with a rollback to a risky transformation to preserve correctness. Highlights include a Y*(X+1) -> X*Y+Y transformation pass for MAD-enabled platforms and an i64-to-i32 narrowing optimization; the Y*(X+1) optimization was subsequently reverted, along with its tests, to stabilize canonicalization paths. Overall impact includes potential single-instruction mapping on supported hardware, reduced 64-bit usage, and improved test hygiene.
October 2025
3 Commits • 1 Features
Oct 1, 2025October 2025 monthly recap for intel/intel-graphics-compiler: Delivered targeted performance optimizations and 64-bit narrowing in codegen, with a rollback to a risky transformation to preserve correctness. Highlights include a Y*(X+1) -> X*Y+Y transformation pass for MAD-enabled platforms and an i64-to-i32 narrowing optimization; the Y*(X+1) optimization was subsequently reverted, along with its tests, to stabilize canonicalization paths. Overall impact includes potential single-instruction mapping on supported hardware, reduced 64-bit usage, and improved test hygiene.
September 2025
1 Commits • 1 Features
Sep 1, 2025September 2025 monthly summary for the intel/intel-graphics-compiler project, focusing on a compute-oriented vector optimization delivered to improve throughput for large insertelement workloads.
1 Commits • 1 Features
Sep 1, 2025September 2025 monthly summary for the intel/intel-graphics-compiler project, focusing on a compute-oriented vector optimization delivered to improve throughput for large insertelement workloads.
September 2025
August 2025
4 Commits • 2 Features
Aug 1, 2025Monthly work summary for 2025-08 (intel/intel-graphics-compiler) Key features delivered: - PVC Platform Payload Header Optimization: Enabled ShortImplicitPayloadHeader on PVC, removing unused fields and simplifying compute workload arguments. Result: reduced header overhead and improved payload processing efficiency. - SIMD32 Kernel Enhancements: Implemented 2D block I/O (SPIR-V APIs for 2D block load, store, and prefetch) and DPAS support for 32n16 configurations; introduced Code Scheduling LIT to improve kernel throughput. Major bugs fixed: - Test-related fixes for SIMD32 changes to stabilize verification and ensure reliable validation of new features. Overall impact and accomplishments: - Improved payload efficiency and SIMD32 kernel performance, translating to higher throughput and lower latency for critical graphics workloads. - Expanded test coverage and scheduling capabilities, enabling faster iteration and greater confidence in future optimizations. Technologies/skills demonstrated: - SPIR-V 2D I/O, DPAS, ShortImplicitPayloadHeader optimization, Code Scheduling LIT, test automation, performance-oriented kernel development. Month: 2025-08 Repository: intel/intel-graphics-compiler
August 2025
4 Commits • 2 Features
Aug 1, 2025Monthly work summary for 2025-08 (intel/intel-graphics-compiler) Key features delivered: - PVC Platform Payload Header Optimization: Enabled ShortImplicitPayloadHeader on PVC, removing unused fields and simplifying compute workload arguments. Result: reduced header overhead and improved payload processing efficiency. - SIMD32 Kernel Enhancements: Implemented 2D block I/O (SPIR-V APIs for 2D block load, store, and prefetch) and DPAS support for 32n16 configurations; introduced Code Scheduling LIT to improve kernel throughput. Major bugs fixed: - Test-related fixes for SIMD32 changes to stabilize verification and ensure reliable validation of new features. Overall impact and accomplishments: - Improved payload efficiency and SIMD32 kernel performance, translating to higher throughput and lower latency for critical graphics workloads. - Expanded test coverage and scheduling capabilities, enabling faster iteration and greater confidence in future optimizations. Technologies/skills demonstrated: - SPIR-V 2D I/O, DPAS, ShortImplicitPayloadHeader optimization, Code Scheduling LIT, test automation, performance-oriented kernel development. Month: 2025-08 Repository: intel/intel-graphics-compiler
July 2025
3 Commits
Jul 1, 2025Month: 2025-07 — Focused on correctness and memory handling in the intel-graphics-compiler. Delivered targeted bug fixes in critical code paths to stabilize optimization decisions and memory operations. No new features released this month; maintenance work reduces risk and establishes a solid foundation for upcoming performance improvements. Technologies/skills demonstrated include C++, LLVM-based analysis, SCEV reasoning, and GRF-aware memory layout.
3 Commits
Jul 1, 2025Month: 2025-07 — Focused on correctness and memory handling in the intel-graphics-compiler. Delivered targeted bug fixes in critical code paths to stabilize optimization decisions and memory operations. No new features released this month; maintenance work reduces risk and establishes a solid foundation for upcoming performance improvements. Technologies/skills demonstrated include C++, LLVM-based analysis, SCEV reasoning, and GRF-aware memory layout.
July 2025
June 2025
1 Commits • 1 Features
Jun 1, 2025June 2025: Implemented a performance optimization for the bitselect intrinsic in intel/intel-graphics-compiler by routing bitselect to a single bfn instruction when the UseBfn flag is enabled. This provides a hardware-accelerated path for SPIR-V/OpenCL C bitselect, reducing instruction count and improving runtime throughput for affected workloads. Commits: b949e1fca701e1cd17a1c9c6fa0d87526918e4e9 ("Optimize SPIR-V / OpenCL C \"bitselect\" builtin function (2nd)"). No major bugs fixed this month; focus was on feature delivery and integration. Overall impact: stronger performance for bit-level operations and better alignment with performance goals. Technologies/skills demonstrated: SPIR-V, OpenCL C, intrinsic optimization, UseBfn flag, code review and commit-based delivery.
June 2025
1 Commits • 1 Features
Jun 1, 2025June 2025: Implemented a performance optimization for the bitselect intrinsic in intel/intel-graphics-compiler by routing bitselect to a single bfn instruction when the UseBfn flag is enabled. This provides a hardware-accelerated path for SPIR-V/OpenCL C bitselect, reducing instruction count and improving runtime throughput for affected workloads. Commits: b949e1fca701e1cd17a1c9c6fa0d87526918e4e9 ("Optimize SPIR-V / OpenCL C \"bitselect\" builtin function (2nd)"). No major bugs fixed this month; focus was on feature delivery and integration. Overall impact: stronger performance for bit-level operations and better alignment with performance goals. Technologies/skills demonstrated: SPIR-V, OpenCL C, intrinsic optimization, UseBfn flag, code review and commit-based delivery.
May 2025
4 Commits • 1 Features
May 1, 2025May 2025 monthly summary for intel/intel-graphics-compiler focusing on stability, correctness, and selective performance improvements through guarded optimizations.
4 Commits • 1 Features
May 1, 2025May 2025 monthly summary for intel/intel-graphics-compiler focusing on stability, correctness, and selective performance improvements through guarded optimizations.
May 2025
April 2025
6 Commits • 1 Features
Apr 1, 2025April 2025 monthly summary for intel/intel-graphics-compiler: Delivered consolidated management of implicit argument optimization flags with safe defaults and platform-aware checks, including refactoring to disable optimizations when legacy bindless is used and reverting to prior behavior when necessary to preserve stability. Fixed critical issues affecting shader correctness and large-buffer OpenCL workloads: (1) ensured bindless optimizations are disabled when -cl-intel-greater-than-4GB-buffer-required is active, and (2) aligned uniform prefetch source addresses to GRF boundaries for correctness and stability. These changes improve correctness, stability, and predictability of shader compilation across GPU generations, reducing risk of unintended optimizations and memory misalignment. Demonstrated solid technical execution across C++ refactoring, feature-flag driven logic, platform-specific handling, and memory alignment concerns, contributing to robust OpenCL shader support and maintainable code.
April 2025
6 Commits • 1 Features
Apr 1, 2025April 2025 monthly summary for intel/intel-graphics-compiler: Delivered consolidated management of implicit argument optimization flags with safe defaults and platform-aware checks, including refactoring to disable optimizations when legacy bindless is used and reverting to prior behavior when necessary to preserve stability. Fixed critical issues affecting shader correctness and large-buffer OpenCL workloads: (1) ensured bindless optimizations are disabled when -cl-intel-greater-than-4GB-buffer-required is active, and (2) aligned uniform prefetch source addresses to GRF boundaries for correctness and stability. These changes improve correctness, stability, and predictability of shader compilation across GPU generations, reducing risk of unintended optimizations and memory misalignment. Demonstrated solid technical execution across C++ refactoring, feature-flag driven logic, platform-specific handling, and memory alignment concerns, contributing to robust OpenCL shader support and maintainable code.
March 2025
17 Commits • 2 Features
Mar 1, 2025March 2025 performance and reliability improvements in the intel-graphics-compiler: delivered core payload header optimization and implicit-argument cleanup across Xe generations, with per-core enablement, correctness safeguards, and test robustness enhancements. These changes reduce kernel argument footprints and improve runtime performance and binary size while strengthening validation across Xe1–Xe3.
17 Commits • 2 Features
Mar 1, 2025March 2025 performance and reliability improvements in the intel-graphics-compiler: delivered core payload header optimization and implicit-argument cleanup across Xe generations, with per-core enablement, correctness safeguards, and test robustness enhancements. These changes reduce kernel argument footprints and improve runtime performance and binary size while strengthening validation across Xe1–Xe3.
March 2025
February 2025
8 Commits • 3 Features
Feb 1, 2025February 2025: Delivered targeted optimizations and architectural improvements in intel/intel-graphics-compiler, focusing on pointer arithmetic optimization, kernel payload footprint, and 64-bit get_global_id support. These changes improved kernel performance, reduced memory usage, and increased robustness across 32- and 64-bit workloads.
February 2025
8 Commits • 3 Features
Feb 1, 2025February 2025: Delivered targeted optimizations and architectural improvements in intel/intel-graphics-compiler, focusing on pointer arithmetic optimization, kernel payload footprint, and 64-bit get_global_id support. These changes improved kernel performance, reduced memory usage, and increased robustness across 32- and 64-bit workloads.
January 2025
2 Commits • 2 Features
Jan 1, 2025Month: 2025-01 | Intel Graphics Compiler — key deliverables focused on correctness and stability, with measurable business impact. Key features delivered: - Robust indirect memory access analysis in ScalarArgAsPointerAnalysis: improved operand tracing for SelectInst and GetElementPtrInst, simplified logic, and more robust handling of indirect memory accesses. Also incremented version number for indirect access detection. Commit: 8e40147e3f43a52c1f139fc0a67854fcfb75f032. - Stabilize Loop Strength Reduction by disabling experimental features by default: reduce risk from experimental LSR features by defaulting EnableGEPLSRMulExpr and EnableGEPLSRUnknownConstantStep to off; updated tests to explicitly enable EnableGEPLSRMulExpr where needed. Commit: 3fc46098a6c71833bb99ce96b5c0b4b22b02dabb. Major bugs fixed / stability improvements: - Reduced risk and potential instability from experimental LSR paths by defaulting them off and updating tests accordingly, leading to more predictable builds and fewer flaky tests. Overall impact and accomplishments: - Improved correctness and robustness of memory analysis in code generation paths, with a safer default behavior for LSR features. - Maintained momentum with targeted refactoring and test coverage, enabling smoother future feature work and easier maintenance. - Version increment signals maintenance of indirect access diagnostics for downstream tooling. Technologies/skills demonstrated: - LLVM/Clang-style pass development, especially ScalarArgAsPointerAnalysis and Loop Strength Reduction (LSR). - Refactoring for clarity and robustness, feature toggling, test maintenance, and versioning.
2 Commits • 2 Features
Jan 1, 2025Month: 2025-01 | Intel Graphics Compiler — key deliverables focused on correctness and stability, with measurable business impact. Key features delivered: - Robust indirect memory access analysis in ScalarArgAsPointerAnalysis: improved operand tracing for SelectInst and GetElementPtrInst, simplified logic, and more robust handling of indirect memory accesses. Also incremented version number for indirect access detection. Commit: 8e40147e3f43a52c1f139fc0a67854fcfb75f032. - Stabilize Loop Strength Reduction by disabling experimental features by default: reduce risk from experimental LSR features by defaulting EnableGEPLSRMulExpr and EnableGEPLSRUnknownConstantStep to off; updated tests to explicitly enable EnableGEPLSRMulExpr where needed. Commit: 3fc46098a6c71833bb99ce96b5c0b4b22b02dabb. Major bugs fixed / stability improvements: - Reduced risk and potential instability from experimental LSR paths by defaulting them off and updating tests accordingly, leading to more predictable builds and fewer flaky tests. Overall impact and accomplishments: - Improved correctness and robustness of memory analysis in code generation paths, with a safer default behavior for LSR features. - Maintained momentum with targeted refactoring and test coverage, enabling smoother future feature work and easier maintenance. - Version increment signals maintenance of indirect access diagnostics for downstream tooling. Technologies/skills demonstrated: - LLVM/Clang-style pass development, especially ScalarArgAsPointerAnalysis and Loop Strength Reduction (LSR). - Refactoring for clarity and robustness, feature toggling, test maintenance, and versioning.
January 2025
December 2024
13 Commits • 5 Features
Dec 1, 2024December 2024 performance month for intel/intel-graphics-compiler: focused on delivering high-value features and robustness improvements to shader/OpenCL work, while tightening correctness in divergent paths. Key outcomes include clustered subgroup intrinsics, subgroup sort performance enhancements, robust defaults for optimization passes, and compute workload packing optimization, plus a critical correctness fix in indirect access detection across divergent code paths.
December 2024
13 Commits • 5 Features
Dec 1, 2024December 2024 performance month for intel/intel-graphics-compiler: focused on delivering high-value features and robustness improvements to shader/OpenCL work, while tightening correctness in divergent paths. Key outcomes include clustered subgroup intrinsics, subgroup sort performance enhancements, robust defaults for optimization passes, and compute workload packing optimization, plus a critical correctness fix in indirect access detection across divergent code paths.
November 2024
6 Commits • 2 Features
Nov 1, 2024Month: 2024-11 – Focused on performance optimization and GPU-subgroup enhancements in intel/intel-graphics-compiler. Delivered a prototype to cache ZExt/SExt SCEV expressions to reduce redundant work and accelerate compilation, with enhanced verification. Implemented clustered intrinsics for subgroup operations to improve parallelism and throughput. Maintained stability by reverting the ZExt/SExt SCEV caching path after verification failures and performance regressions.
6 Commits • 2 Features
Nov 1, 2024Month: 2024-11 – Focused on performance optimization and GPU-subgroup enhancements in intel/intel-graphics-compiler. Delivered a prototype to cache ZExt/SExt SCEV expressions to reduce redundant work and accelerate compilation, with enhanced verification. Implemented clustered intrinsics for subgroup operations to improve parallelism and throughput. Maintained stability by reverting the ZExt/SExt SCEV caching path after verification failures and performance regressions.
November 2024
October 2024
1 Commits • 1 Features
Oct 1, 2024October 2024 (2024-10): Delivered a performance-oriented improvement to intel/intel-graphics-compiler by implementing a caching layer for Zero Extend (ZExt) SCEV expressions. This change, paired with verification enhancements to ensure cache integrity, reduces redundant ZExt computations in builds with extensive ZExt usage and speeds up compile times. It demonstrates solid involvement in compiler infrastructure, caching strategies, and verification workflows, and strengthens the reliability of the SCEV/IR pipeline.
October 2024
1 Commits • 1 Features
Oct 1, 2024October 2024 (2024-10): Delivered a performance-oriented improvement to intel/intel-graphics-compiler by implementing a caching layer for Zero Extend (ZExt) SCEV expressions. This change, paired with verification enhancements to ensure cache integrity, reduces redundant ZExt computations in builds with extensive ZExt usage and speeds up compile times. It demonstrates solid involvement in compiler infrastructure, caching strategies, and verification workflows, and strengthens the reliability of the SCEV/IR pipeline.
September 2024
1 Commits • 1 Features
Sep 1, 2024Summary for 2024-09: Delivered IndVarSimplification pass for OpenCL shader optimization in the Intel Graphics Compiler, enabling more aggressive induction-variable simplifications and potential OpenCL shader performance gains. No major bugs fixed this month. Impact: enhances the compiler's optimization capabilities for OpenCL shaders, setting up for further performance improvements. Technologies/skills: compiler optimization passes, OpenCL shader pipeline, IndVarSimplification, LLVM-based optimizations, Git-based change management.
1 Commits • 1 Features
Sep 1, 2024Summary for 2024-09: Delivered IndVarSimplification pass for OpenCL shader optimization in the Intel Graphics Compiler, enabling more aggressive induction-variable simplifications and potential OpenCL shader performance gains. No major bugs fixed this month. Impact: enhances the compiler's optimization capabilities for OpenCL shaders, setting up for further performance improvements. Technologies/skills: compiler optimization passes, OpenCL shader pipeline, IndVarSimplification, LLVM-based optimizations, Git-based change management.
September 2024
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Quality Metrics
Correctness89.6%
Maintainability87.2%
Architecture86.2%
Performance84.4%
AI Usage20.2%
Skills & Technologies
Programming Languages
CC++CLLLVMLLVM IROpenCLOpenCL CYAML
Technical Skills
API DesignBug FixingBuild System ConfigurationBuild SystemsC++C++ developmentC++ programmingCode AnalysisCode GenerationCode OptimizationCode RefactoringCode RevertingCompiler DesignCompiler DevelopmentCompiler Optimization
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