During December 2024, Pavel Penzin developed a base scheduling model for the RISC-V tt-ascalon-d8 processor in the espressif/llvm-project repository. He defined processor resources, instruction latencies, and resource usage for arithmetic, memory, and conversion operations, enabling LLVM MCA to simulate and analyze performance characteristics specific to this architecture. Working primarily in C++ and leveraging expertise in compiler development and performance analysis, Pavel’s contribution established a foundation for accurate resource and latency modeling. This work supports future profiling and optimization workflows, addressing the need for precise performance modeling in RISC-V architecture and enhancing the project’s ability to guide targeted optimizations.