Developed and delivered a base scheduling model for the RISC-V tt-ascalon-d8 processor within the espressif/llvm-project repository, focusing on accurate modeling of processor resources, instruction latencies, and resource usage for arithmetic, memory, and conversion operations. Integrated this model with LLVM MCA to enable detailed simulation and analysis of performance characteristics, supporting future profiling and optimization workflows. The work involved compiler development and performance analysis using C++ and LLVM, with an emphasis on RISC-V architecture modeling. This feature established a technical foundation for resource and latency modeling, guiding subsequent optimization efforts without addressing major bug fixes during the period.