Worked on performance optimization in the rust-lang/gcc repository, focusing on vector data reduction for AMD znver4 and znver5 processors within the i386 backend. Developed a shift-to-shuffle based reduction path, replacing traditional shift-based reductions with shuffle instructions to better leverage architecture-specific capabilities. This approach improved code generation quality and enhanced performance tuning for AMD architectures. Added an automated test to verify correct shuffle instruction generation, increasing verification coverage. The work involved deep knowledge of assembly language, compiler optimization, and x86 architecture, demonstrating a targeted engineering effort to strengthen backend support for modern AMD processors using C++ and related technologies.