Worked on the gem5/gem5 repository to deliver a key architectural enhancement in the O3 CPU model by refactoring the store set construction to leverage the Generic Cache Library. This approach enabled the use of associative cache structures and multiple replacement policies, increasing the configurability of cache behavior for performance analysis and research. The work centralized store-set logic, improving maintainability and simplifying experimentation with cache configurations. Implemented primarily in C++ and Python, the changes provided a more flexible and testable foundation for CPU and cache simulation, with a focus on system architecture and performance analysis rather than bug fixing during this period.