During June 2025, Pei-Tzu Kuo refactored the sm_bus logic in the stage_top.v module for the vic9112/final_project_2025 repository, focusing on improving data handling and transmission reliability. Leveraging expertise in Digital Logic Design and Hardware Design with Verilog, Pei-Tzu introduced a state machine to the sm_buffer, enabling precise tracking of data occupancy. A sequential counter was also implemented to ensure orderly data output. These enhancements addressed data processing bottlenecks and improved validity signaling, resulting in higher throughput and reduced risk of data loss. The work demonstrated a thoughtful approach to robust hardware design and effective data stream management.