Worked on the Xilinx/mlir-aie repository to enhance the reliability of dataflow operations involving padding scenarios. Focused on correcting MemTile buffer allocation within ObjectFifoLink so that output dimensions accurately reflect applied padding, thereby preventing incorrect buffer sizes during runtime. Used C++ and MLIR to implement the fix and added regression tests in Python to validate ObjectFifo behavior with padded outputs. Collaborated with a co-author to secure cross-team validation, ensuring the solution addressed integration requirements. This work improved test coverage and reduced runtime risk, strengthening the correctness and maintainability of padding paths in the MLIR-AIE integration for future development.