Sam Castleberry enhanced memory subsystem reliability and processor performance by centralizing and expanding SRAM read-write conflict handling in the OpenXiangShan/Utility and OpenXiangShan/XiangShan repositories. He refactored the SRAMTemplate to support multiple conflict resolution strategies, including corrupt reads, buffered writes, and write stalls, while ensuring backward compatibility and comprehensive test coverage. Using Chisel and Scala, Sam’s work reduced frontend complexity and improved instruction per cycle rates and branch prediction accuracy. His approach provided configurable conflict modes for safer dual-port SRAM operations, demonstrating depth in computer architecture, RTL design, and test-driven development, and resulting in measurable architectural and performance improvements.