Developed an LDAPUR atomic load optimization for AArch64 with RCPC2 in the rust-lang/gcc repository, targeting improved performance for atomic operations on RCPC2-enabled ARM cores. The work involved enabling the LDAPUR instruction for atomic loads when RCPC2 is available, folding address computation directly into the addressing mode to reduce instruction count and latency. This optimization was implemented in C and C++, with a new tuning flag allowing selective disablement for configurable performance control. The approach focused on compiler development and performance optimization, aligning with low-latency atomic requirements and providing a safer, default-enabled rollout for targeted ARM architectures.