Month: 2025-11 — Focused on improving interrupt timing and boot-time performance for Apollo4P within the Zephyr RTOS. Delivered early cache initialization in the Apollo4P SoC boot sequence to enable proper timing at 96 MHz, aligning with Apollo3 init and Ambiq SDK expectations. This change fixes interrupt timing delays observed in time-critical UART TDMA workflows (2 Mbaud, 1 ms frame timing) by ensuring cache is configured and enabled early, prior to low-power init, reducing latency by hundreds of microseconds and improving determinism in high-speed serial operations. The work enhances system reliability, performance, and consistency across latency-sensitive tasks, and sets the foundation for future optimizations at the Apollo4P platform while maintaining alignment with official SDK guidance.