
Tomasz Michalak contributed to hardware verification and digital design projects, focusing on the antmicro/Cores-VeeR-EL2 and chipsalliance/i3c-core repositories. He enhanced CI/CD pipelines and test automation using Python and Makefile, improving simulation reliability and feedback cycles. His work included patching AXI slave read path correctness, expanding privilege-level testing for RISC-V Debugger, and integrating DPI sources for more accurate simulations. Tomasz also documented AXI Streaming Boot workflows in chipsalliance/caliptra-ss, clarifying integration steps and compliance requirements. His approach emphasized maintainable, traceable changes and robust verification, resulting in more reliable hardware designs and streamlined onboarding for future contributors.

September 2025 monthly summary focusing on key accomplishments in AXI streaming boot documentation across two repositories (caliptra-ss and i3c-core). The primary emphasis was documenting and clarifying the AXI Streaming Boot workflow to enable faster integration, safer deployments, and ongoing compliance with Caliptra requirements. Key commit references are noted for traceability.
September 2025 monthly summary focusing on key accomplishments in AXI streaming boot documentation across two repositories (caliptra-ss and i3c-core). The primary emphasis was documenting and clarifying the AXI Streaming Boot workflow to enable faster integration, safer deployments, and ongoing compliance with Caliptra requirements. Key commit references are noted for traceability.
February 2025: Strengthened verification, CI automation, and debugging capabilities for RISC-V and EL2 designs. Delivered granular privilege-level testing, enhanced DPI-enabled simulation, and TAP FSM validation with VCD support. No major bugs fixed this month; primary business value comes from expanded test coverage, faster issue diagnosis, and higher confidence in design correctness across two repositories.
February 2025: Strengthened verification, CI automation, and debugging capabilities for RISC-V and EL2 designs. Delivered granular privilege-level testing, enhanced DPI-enabled simulation, and TAP FSM validation with VCD support. No major bugs fixed this month; primary business value comes from expanded test coverage, faster issue diagnosis, and higher confidence in design correctness across two repositories.
January 2025 monthly summary for antmicro/Cores-VeeR-EL2: Delivered PMP verification enhancements and testbench quality improvements alongside CI/CD and test infrastructure upgrades to enable reliable hardware validation and faster iteration. The work focused on improving verification coverage and stability for dec_pmp_ctl, strengthening test scaffolds, and modernizing CI pipelines and simulation tooling. These efforts reduce risk in releases and improve confidence in hardware behavior before integration.
January 2025 monthly summary for antmicro/Cores-VeeR-EL2: Delivered PMP verification enhancements and testbench quality improvements alongside CI/CD and test infrastructure upgrades to enable reliable hardware validation and faster iteration. The work focused on improving verification coverage and stability for dec_pmp_ctl, strengthening test scaffolds, and modernizing CI pipelines and simulation tooling. These efforts reduce risk in releases and improve confidence in hardware behavior before integration.
December 2024 monthly summary for antmicro/Cores-VeeR-EL2: Key feature delivered: Implemented a correctness-focused fix in the AXI slave read path by introducing a read_address and assigning it from araddr when arvalid and arready are asserted. This ensures the read uses a legal index value, strengthening the reliability of memory-read operations in the AXI interface. Major bugs fixed: Read address legality bug in the AXI slave (axi_slv) module was addressed, eliminating a potential source of invalid memory reads during AR handshake and improving overall memory access correctness. Performance, reliability, and business value: The fix reduces risk of invalid memory reads, leading to more deterministic behavior in SoC integrations and faster hardware bring-up. This contributes to system stability for dependent peripherals and higher confidence when integrating the EL2 core into customer designs. Technologies/skills demonstrated: AXI protocol debugging and RTL-level patching, handshake-based read path correction, verification-oriented development (aligned with AHb SIF verification updates), commit-based traceability for changes.
December 2024 monthly summary for antmicro/Cores-VeeR-EL2: Key feature delivered: Implemented a correctness-focused fix in the AXI slave read path by introducing a read_address and assigning it from araddr when arvalid and arready are asserted. This ensures the read uses a legal index value, strengthening the reliability of memory-read operations in the AXI interface. Major bugs fixed: Read address legality bug in the AXI slave (axi_slv) module was addressed, eliminating a potential source of invalid memory reads during AR handshake and improving overall memory access correctness. Performance, reliability, and business value: The fix reduces risk of invalid memory reads, leading to more deterministic behavior in SoC integrations and faster hardware bring-up. This contributes to system stability for dependent peripherals and higher confidence when integrating the EL2 core into customer designs. Technologies/skills demonstrated: AXI protocol debugging and RTL-level patching, handshake-based read path correction, verification-oriented development (aligned with AHb SIF verification updates), commit-based traceability for changes.
November 2024 focused on delivering business value through CI efficiency and protocol simulation reliability. Delivered two targeted changes across two repositories that reduce CI noise, improve feedback loops, and increase simulation correctness. Result: faster iteration cycles, lower CI costs, and more reliable hardware protocol tests. Demonstrated skills include CI/CD optimization, Reviewdog configuration, Git submodule management, and cocotb-based hardware verification.
November 2024 focused on delivering business value through CI efficiency and protocol simulation reliability. Delivered two targeted changes across two repositories that reduce CI noise, improve feedback loops, and increase simulation correctness. Result: faster iteration cycles, lower CI costs, and more reliable hardware protocol tests. Demonstrated skills include CI/CD optimization, Reviewdog configuration, Git submodule management, and cocotb-based hardware verification.
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