Developed a design verification enhancement for the lowRISC/opentitan repository by extending the OTBN DV environment to support WDR (Write Data Register) address fields. This addition enabled precise traceability of write data registers during verification, streamlining defect localization and simplifying debugging for OTBN-related changes. The work was implemented as a single patch using SystemVerilog and UVM, demonstrating skills in hardware verification and environment customization. By integrating the enhancement and validating it within existing DV workflows, the developer improved verification cycle efficiency and traceability. The approach emphasized traceability engineering and effective Git-based change management, contributing to more robust hardware verification processes.