OpenXiangShan/XiangShan
Jan 2026 – Jan 2026
1 Month active
Languages Used
MakefileScala
Technical Skills
CI/CDScalafull stack developmenthardware simulation
高睿昊
PROFILE
高睿昊
Overall Statistics
Feature vs Bugs
100%Features
Repository Contributions
1Total
Bugs
0
Commits
1
Features
1
Lines of code
109
Activity Months1
Your Network
53 people
Work History
January 2026
1 Commits • 1 Features
Jan 1, 2026January 2026 monthly summary for OpenXiangShan/XiangShan focused on enabling GSIM integration with Chisel 7.3.0. Delivered GSIM support with new build steps and enhanced memory request handling, strengthening hardware-software co-simulation capabilities. Validated Linux boot in GSIM mode (make gsim-run GSIM=1 -j 30), confirming end-to-end verification flow. Initiated Makefile restructuring considerations to isolate GSIM targets, reducing cross-target interference and easing future testing. Collaboration spanned multiple contributors (co-authored commits), accelerating integration.
1 Commits • 1 Features
Jan 1, 2026January 2026 monthly summary for OpenXiangShan/XiangShan focused on enabling GSIM integration with Chisel 7.3.0. Delivered GSIM support with new build steps and enhanced memory request handling, strengthening hardware-software co-simulation capabilities. Validated Linux boot in GSIM mode (make gsim-run GSIM=1 -j 30), confirming end-to-end verification flow. Initiated Makefile restructuring considerations to isolate GSIM targets, reducing cross-target interference and easing future testing. Collaboration spanned multiple contributors (co-authored commits), accelerating integration.
January 2026
Activity
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Quality Metrics
Correctness80.0%
Maintainability80.0%
Architecture80.0%
Performance80.0%
AI Usage40.0%
Skills & Technologies
Programming Languages
MakefileScala
Technical Skills
CI/CDScalafull stack developmenthardware simulation
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