During August 2025, Zhanghongce contributed to the YosysHQ/yosys repository by implementing a deterministic port dump order in the Verilog backend. This work involved refactoring backend code in C++ and Verilog to ensure module ports are output in their defined order, addressing issues of nondeterminism and duplicate outputs in generated Verilog files. By aligning the backend’s wire dumping logic with repository guidelines and responding to code review feedback, Zhanghongce improved the maintainability and readability of the codebase. These changes enhanced the reliability and reproducibility of Verilog output, supporting more predictable builds for downstream toolchains and simplifying debugging.