OpenXiangShan-Nanhu/Nanhu-V5
Nov 2024 – Jun 2025
3 Months active
Languages Used
ChiselScala
Technical Skills
CPU ArchitectureCPU DesignComputer ArchitectureHardware DesignRISC-VRISC-V Architecture
Jinghui-Z
PROFILE
Jinghui-z
Over three months, this developer enhanced the OpenXiangShan-Nanhu/Nanhu-V5 CPU core by refining instruction fetch and cache coherence mechanisms. They streamlined the Front-End Queue logic and branch prediction, reducing mispredictions and improving fetch reliability using Chisel and Verilog. Their work on the IFU pipeline introduced register duplication to lower fanout and increased robustness during instruction validation and flushing. Additionally, they addressed ICache timing by enabling MSHR responses during flushes, preventing pipeline stalls. By removing redundant flush logic and distinguishing IFU versus backend cache paths, they improved redirect handling and cache coherence, demonstrating depth in CPU architecture and digital logic design.
Overall Statistics
Feature vs Bugs
40%Features
Repository Contributions
8Total
Bugs
3
Commits
8
Features
2
Lines of code
863
Activity Months3
Your Network
20 people
Work History
June 2025
2 Commits
Jun 1, 2025June 2025 (OpenXiangShan-Nanhu/Nanhu-V5): CPU flush logic correctness improvements focusing on reducing race conditions and invalidations during redirects. Implemented targeted fixes: removed redundant BPU flush logic in the IFU and refined ICache flush behavior to distinguish IFU vs backend paths, preserving softPrefetches during IFU redirects. Result: stabilized redirect handling, improved cache coherence, and reduced flush-related overhead across workloads.
2 Commits
Jun 1, 2025June 2025 (OpenXiangShan-Nanhu/Nanhu-V5): CPU flush logic correctness improvements focusing on reducing race conditions and invalidations during redirects. Implemented targeted fixes: removed redundant BPU flush logic in the IFU and refined ICache flush behavior to distinguish IFU vs backend paths, preserving softPrefetches during IFU redirects. Result: stabilized redirect handling, improved cache coherence, and reduced flush-related overhead across workloads.
June 2025
January 2025
2 Commits • 1 Features
Jan 1, 2025January 2025 monthly summary for OpenXiangShan-Nanhu/Nanhu-V5. Focused on delivering robust IFU behavior and stabilizing the ICache path under flush conditions, with clear commit traceability.
January 2025
2 Commits • 1 Features
Jan 1, 2025January 2025 monthly summary for OpenXiangShan-Nanhu/Nanhu-V5. Focused on delivering robust IFU behavior and stabilizing the ICache path under flush conditions, with clear commit traceability.
November 2024
4 Commits • 1 Features
Nov 1, 2024Month: 2024-11 | Repository: OpenXiangShan-Nanhu/Nanhu-V5 Focused on core FTQ optimization and branch-prediction stability to boost instruction fetch efficiency and runtime reliability. Deliverables emphasize business value through cleaner FTQ logic, reduced mispredictions, and actionable traceability.
4 Commits • 1 Features
Nov 1, 2024Month: 2024-11 | Repository: OpenXiangShan-Nanhu/Nanhu-V5 Focused on core FTQ optimization and branch-prediction stability to boost instruction fetch efficiency and runtime reliability. Deliverables emphasize business value through cleaner FTQ logic, reduced mispredictions, and actionable traceability.
November 2024
Activity
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Quality Metrics
Correctness81.2%
Maintainability81.2%
Architecture80.0%
Performance77.6%
AI Usage20.0%
Skills & Technologies
Programming Languages
ChiselScala
Technical Skills
CPU ArchitectureCPU DesignCache CoherenceCache CoherencyComputer ArchitectureDigital Logic DesignHardware DesignRISC-VRISC-V ArchitectureTiming AnalysisVerilog/ChiselVerilog/SystemVerilog (implied by context)
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