OpenXiangShan-Nanhu/Nanhu-V5
Nov 2024 – Dec 2024
2 Months active
Languages Used
Scala
Technical Skills
Cache CoherenceCache Coherence ProtocolsDigital Logic DesignHardware DesignSystem ArchitectureSystem-on-Chip (SoC) Design
chen kangping
PROFILE
Chen Kangping
During two months contributing to OpenXiangShan-Nanhu/Nanhu-V5, Chenkangping enhanced the DCache data path and stabilized in-flight data handling. They refactored DCacheToSbufferIO and MainPipe logic to improve data flow and memory coherence, introducing GrantDataQueue and SRAMQueue for efficient TL Grant message processing. Using Verilog, Chisel, and Scala, Chenkangping addressed critical bugs in MissQueue forward tracking and Sbuffer area reduction, ensuring correct in-flight request matching and reliable tag management. Their work focused on cache coherence protocols and low-level hardware design, delivering targeted improvements that reduced replay risk, simplified maintenance, and restored correctness in complex System-on-Chip data paths.
Overall Statistics
Feature vs Bugs
40%Features
Repository Contributions
6Total
Bugs
3
Commits
6
Features
2
Lines of code
1,711
Activity Months2
Your Network
22 peopleSame Organization
@open02.boscszcluster.com2
Work History
December 2024
1 Commits
Dec 1, 2024December 2024 monthly summary for OpenXiangShan-Nanhu/Nanhu-V5. The month focused on stabilizing the Sbuffer inflight path by delivering a targeted bug fix to the area reduction logic. The fix simplifies inflight mask and data selection by using the computed inflight_tag_matches directly, correcting erroneous behavior introduced by area reduction. This change restores correctness in in-flight processing and reduces the risk of data-path anomalies.
1 Commits
Dec 1, 2024December 2024 monthly summary for OpenXiangShan-Nanhu/Nanhu-V5. The month focused on stabilizing the Sbuffer inflight path by delivering a targeted bug fix to the area reduction logic. The fix simplifies inflight mask and data selection by using the computed inflight_tag_matches directly, correcting erroneous behavior introduced by area reduction. This change restores correctness in in-flight processing and reduces the risk of data-path anomalies.
December 2024
November 2024
5 Commits • 2 Features
Nov 1, 2024Concise monthly summary for 2024-11 focused on delivering value and strengthening reliability for the Nanhu-V5 DCache path. This month delivered key features to improve data-path integrity, introduced new queueing for TL grants, and fixed critical in-flight and probe replay issues. The work enhances data integrity, memory coherence, and system throughput, while reducing replay-related risk and simplifying maintenance across the DCache, Sbuffer, and TL channels.
November 2024
5 Commits • 2 Features
Nov 1, 2024Concise monthly summary for 2024-11 focused on delivering value and strengthening reliability for the Nanhu-V5 DCache path. This month delivered key features to improve data-path integrity, introduced new queueing for TL grants, and fixed critical in-flight and probe replay issues. The work enhances data integrity, memory coherence, and system throughput, while reducing replay-related risk and simplifying maintenance across the DCache, Sbuffer, and TL channels.
Activity
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Quality Metrics
Correctness85.0%
Maintainability80.0%
Architecture78.4%
Performance71.6%
AI Usage20.0%
Skills & Technologies
Programming Languages
Scala
Technical Skills
Cache CoherenceCache Coherence ProtocolsDigital Logic DesignHardware DesignLow-level ProgrammingSystem ArchitectureSystem-on-Chip (SoC) DesignSystem-on-Chip DesignVerilog/Chisel
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