Worked on the riscv/sail-riscv repository to enhance reliability and maintainability in interrupt handling for embedded systems. Focused on low-level programming using the Sail language, the work involved fixing the MTI and STI pending bit logic within the clint_dispatch function. By reducing redundant conditional checks and consolidating multiple log messages into a single, informative output, the changes improved system observability and diagnostics. The streamlined logic not only ensured correct interrupt dispatch behavior but also made future maintenance simpler, all while maintaining minimal performance overhead. This contribution reflects a methodical approach to system simulation and embedded software reliability within the project.